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US RE41,031 E1Granted
Frequency control system that stabilizes an output through both a counter and voltage-controlled oscillator via sampling a generated clock into four states
OwnerJacques Majosinventor
Life of this patent
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Abstract
A frequency control system includes a voltage-controlled oscillator, a sampling circuit for sampling a clock signal produced by the oscillator for two consecutive transitions of an unstable incoming digital signal, and a frequency comparator for incrementing and decrementing a transition upcounter-downcounter controlling the oscillator. The system tolerates variation of the frequency of the incoming signal about a mean value, which has no effect on a clock signal to be extracted by means of a phase comparator or on the synthesized clock signal supplied by the oscillator if the incoming signal contains a high level of jitter and is supplied by a programmable frequency divider.
Claims56
A frequency control system comprising:
- voltage-controlled oscillator means for generating a clock signal, ;
- means for receiving a digital incoming signal with unstable frequency for sampling said clock signal at two pairs of times corresponding to two consecutive transitions of said incoming signal in response to each of predetermined transitions of said incoming signal, said times of one pair being separated by a predetermined time-delay at most equal to half the period of said clock signal, to produce four state signals of said clock signal, ;
- a frequency comparator for combining said four state signals to form an upcounting signal only in response to the frequency of said clock signal being substantially less than the frequency of said incoming signal and to form a downcounting signal only in response to the frequency of said clock signal being greater than the frequency of said incoming signal, ;
- and
- upcounting and downcounting means for respectively upcounting and downcounting predetermined transitions of said incoming signal in response to said upcounting signal and said downcounting signal for applying a control voltage dependent on a content of said upcounting and downcounting means to said oscillator means via a digital-to-analog converter.
2 more elements
A frequency control signals system comprising:
- a voltage-controlled oscillator for generating a clock signal, ;
- a sampler for receiving a digital input signal having an unstable frequency and for sampling said clock signal at two pairs of times corresponding to two consecutive transitions of said digital input signal, the sampler in response to being arranged to derive four state signals of said clock signal in response to predetermined transitions of said digital input signal, said times of one pair being separated by a predetermined time-delay at most equal to half the period of said clock signal, ;
- a frequency comparator for combining said four state signals to form an upcounting signal only in response to the frequency of said clock signal being substantially less than the frequency of said digital input signal and to form a downcounting signal only in response to the frequency of said clock signal being greater than the frequency of said incoming digital input signal, ;
- and
- a counter for respectively upcounting and downcounting predetermined transitions of said digital input signal in response to said upcounting signal and said downcounting signal, ;
- and
- a converter responsive to the counter for deriving a control voltage dependent on the count of said counter, the oscillator being arranged to be responsive to the control voltage.
4 more elements
A system comprising:
- a frequency comparator;
- a sampling circuit configured to receive a clock signal and a digital input signal and to output at least four sample values to the frequency comparator in response to each transition of a plurality of transitions of the digital input signal, wherein each of said sample values is a sample of the clock signal;
- a counter configured to change a count value in response to transitions of said plurality of transitions, wherein the frequency comparator is configured to operate on said sample values in order to generate one or more control signals that determine whether the counter increases or decreases the count value in response to a transition of said plurality of transitions;
- a voltage-controlled oscillator configured to generate the clock signal with a frequency determined by the count value.
1 more element
A system comprising:
- a frequency comparator;
- a sampling circuit configured to receive a first clock signal and a digital input signal and to output at least four sample values to the frequency comparator in response to each transition of a plurality of transitions of the digital input signal, wherein each of said sample values is a sample of the first clock signal;
- a counter configured to change a count value in response to transitions of said plurality of transitions, wherein the frequency comparator is configured to operate on said sample values in order to generate one or more control signals that determine whether the counter increases or decreases the count value in response to a transition of said plurality of transitions;
- a voltage-controlled oscillator configured to generate a second clock signal with a frequency determined by the count value, wherein the first clock signal has a frequency dependent on the frequency of the second clock signal.
1 more element
A method comprising:
- receiving a clock signal and a digital input signal;
- outputting at least four sample values in response to each transition of a plurality of transitions of the digital input signal, wherein each of said sample values is a sample of the clock signal;
- changing a count value in response to transitions of said plurality of transitions;
- operating on said at least four sample values outputted in response to each transition of said plurality of transitions in order to generate one or more control signals that determine whether the counter increases or decreases the count value in response to a transition of said plurality of transitions;
- generating the clock signal with a frequency determined by the count value.
2 more elements
A method comprising:
- receiving a first clock signal and a digital input signal;
- and
- outputting at least four sample values in response to each transition of a plurality of transitions of the digital input signal, wherein each of said sample values is a sample of the first clock signal;
- changing a count value in response to transitions of said plurality of transitions;
- operating on said at least four sample values outputted in response to each transition of said plurality of transitions in order to generate one or more control signals that determine whether the counter increases or decreases the count value in response to a transition of said plurality of transitions;
- generating a second clock signal with a frequency determined by the count value, wherein the first clock signal has a frequency dependent on the frequency of the second clock signal.
3 more elements
A telecommunication device comprising:
- a frequency comparator;
- a sampling circuit configured to receive a clock signal and a digital input signal and to output at least four sample values to the frequency comparator in response to each transition of a plurality of transitions of the digital input signal, wherein each of said sample values is a sample of the clock signal;
- a counter configured to change a count value in response to transitions of said plurality of transitions, wherein the frequency comparator is configured to operate on said sample values in order to generate one or more control signals that determine whether the counter increases or decreases the count value in response to a transition of said plurality of transitions;
- a voltage-controlled oscillator configured to generate the clock signal with a frequency determined by the count value.
1 more element
A telecommunication device comprising:
- a frequency comparator;
- a sampling circuit configured to receive a first clock signal and a digital input signal and to output at least four sample values to the frequency comparator in response to each transition of a plurality of transitions of the digital input signal, wherein each of said sample values is a sample of the first clock signal;
- a counter configured to change a count value in response to transitions of said plurality of transitions, wherein the frequency comparator is configured to operate on said sample values in order to generate one or more control signals that determine whether the counter increases or decreases the count value in response to a transition of said plurality of transitions;
- a voltage-controlled oscillator configured to generate a second clock signal with a frequency determined by the count value, wherein the first clock signal has a frequency dependent on the frequency of the second clock signal.
1 more element
A system comprising:
- a sampling circuit configured to receive a clock signal and a digital input signal and to output at least four sample values in response to each transition of a plurality of transitions of the digital input signal, wherein each of said sample values is a sample of the clock signal;
- a counter configured to change a count value in response to transitions of said plurality of transitions;
- a frequency comparator that is distinct from the sampling circuit and is configured to operate on said sample values in order to generate one or more control signals that determine whether the counter increases or decreases the count value in response to a transition of said plurality of transitions;
- a voltage-controlled oscillator configured to generate the clock signal with a frequency determined by the count value.
1 more element
A system comprising:
- a sampling circuit configured to receive a first clock signal and a digital input signal and to output at least four sample values in response to each transition of a plurality of transitions of the digital input signal, wherein each of said sample values is a sample of the first clock signal;
- a counter configured to change a count value in response to transitions of said plurality of transitions;
- a frequency comparator that is distinct from the sampling circuit and is configured to operate on said sample values in order to generate one or more control signals that determine whether the counter increases or decreases the count value in response to a transition of said plurality of transitions;
- a voltage-controlled oscillator configured to generate a second clock signal with a frequency determined by the count value, wherein the first clock signal has a frequency dependent on the frequency of the second clock signal.
1 more element
A system comprising:
- a sampling circuit configured to receive a clock signal and a digital input signal and to output at least four sample values in response to each transition of a plurality of transitions of the digital input signal, wherein each of said sample values is a sample of the clock signal;
- decision logic configured to receive said at least four outputted sample values from the sampling circuit and to operate on said at least four outputted sample values in order to generate one or more control signals;
- a counter configured to change a count value in response to transitions of said plurality of transitions, wherein the one or more control signals determine whether the counter increases, decreases or maintains the count value in response to said transition of said plurality of transitions;
- a voltage-controlled oscillator configured to generate the clock signal with a frequency determined by the count value.
1 more element
A system comprising:
- a sampling circuit configured to receive a first clock signal and a digital input signal and to output at least four sample values in response to each transition of a plurality of transitions of the digital input signal, wherein each of said sample values is a sample of the first clock signal;
- decision logic configured to receive said at least four outputted sample values from the sampling circuit and to operate on said at least four outputted sample values in order to generate one or more control signals;
- a counter configured to change a count value in response to transitions of said plurality of transitions, wherein the one or more control signals that determine whether the counter increases, decreases or maintains the count value in response to said transition of said plurality of transitions;
- a voltage-controlled oscillator configured to generate a second clock signal with a frequency determined by the count value, wherein the first clock signal has a frequency dependent on the frequency of the second clock signal.
1 more element
A system comprising:
- a sampling circuit configured to receive a clock signal and a digital input signal and to capture a pair of samples of the clock signal in response to each of a plurality of transitions of the digital input signal, wherein the sampling circuit is configured so that the samples of each pair are separated in time by a fixed delay, wherein the sampling circuit is configured to output a current one and a previous one of said pairs in response to each transition of said plurality of transitions;
- decision logic configured to operate on said current pair and said previous pair of samples in order to generate one or more control values;
- a counter configured to increase, decrease or maintain a count value based on the one or more control values;
- and
- a voltage-controlled oscillator configured to generate the clock signal with a frequency determined by the count value.
2 more elements
A system comprising:
- a sampling circuit configured to receive a first clock signal and a digital input signal and to capture a pair of samples of the first clock signal in response to each of a plurality of transitions of the digital input signal, wherein the sampling circuit is configured so that the samples of each pair are separated in time by a fixed delay, wherein the sampling circuit is configured to output a current one and a previous one of said pairs in response to each transition of said plurality of transitions;
- decision logic configured to operate on said current pair and said previous pair of samples in order to generate one or more control values;
- a counter configured to increase, decrease or maintain a count value based on the one or more control values;
- and
- a voltage-controlled oscillator configured to generate a second clock signal with a frequency determined by the count value, wherein the first clock signal has a frequency dependent on the frequency of the second clock signal.
2 more elements
Dependencies are inferred from the claim text.