Probe card having groups of probe needles in a probing test apparatus for testing semiconductor integrated circuits

A method of testing semiconductor integrated circuit chips, the method comprising:

• coupling each of a plurality of probe contact terminals on a probe card to an independent external tester, the probe card having a plurality of probe needles and each of the plurality of probe contact terminals arranged thereon, wherein the probe contact terminals are direct connected to the probe needles by mechanical wirings;
• preparing a semiconductor wafer having a plurality of semiconductor integrated circuit chips arranged thereon in at least two columns and at least two rows, each of the plurality of semiconductor integrated circuit chips having a plurality of external terminals;
• coupling the plurality of probe needles on the probe card to the plurality of external terminals of each of the plurality of semiconductor integrated circuit chips arranged thereon in at least two columns and at least two rows;
• concurrently receiving a plurality of independent test signals and independent power supply for the probe card by each of the plurality of probe contact terminals from the independent external tester;
• concurrently supplying the plurality of independent test signals and the independent power supply through the plurality of probe needles on the probe card to each of the plurality of semiconductor integrated circuit chips from the probe card;
• concurrently receiving a plurality of independent data output signals of each of the plurality of semiconductor integrated circuit chips in response to the plurality of independent test signals and independent power supply through the plurality of probe needles on the probe card by the probe card;
• concurrently receiving the plurality of independent data output signals of each of the plurality of semiconductor integrated circuit chips through the plurality of probe contact terminals on the probe card by the independent external tester;
• and
• concurrently comparing electrical characteristics of the plurality of independent data output signals of each of the plurality of semiconductor integrated circuit chips by the independent external tester.

A method of testing semiconductor integrated circuit chips, the method comprising:

• coupling a plurality of probe contact terminals on a probe card to an independent external tester, the probe card having a plurality of probe needles and a plurality of probe contact terminals arranged thereon, wherein the probe contact terminals are direct connected to the probe needles by mechanical wirings;
• preparing a semiconductor wafer having a plurality of semiconductor integrated circuit chips arranged thereon in at least two columns and at least two rows, each of the plurality of semiconductor integrated circuit chips having a plurality of external terminals;
• coupling the plurality of probe needles on the probe card to the plurality of external terminals of each of the plurality of semiconductor integrated circuit chips, the plurality of probe needles being arranged on the probe card in at least two columns and at least two rows, the plurality of probe needles corresponding to those of the plurality of external terminals;
• concurrently receiving a plurality of independent test signals and independent power supply for the probe card by each of the plurality of probe contact terminals from the independent external tester;
• concurrently supplying the plurality of independent test signals and the independent power supply through the plurality of probe needles on the probe card to each of the plurality of semiconductor integrated circuit chips from the probe card;
• concurrently receiving a plurality of independent data output signals of each of the plurality of semiconductor integrated circuit chips in response to the plurality of independent test signals and independent power supply through the plurality of probe needles on the probe card by the probe card;
• concurrently receiving the plurality of independent data output signals of each of the plurality of semiconductor integrated circuit chips through the plurality of probe contact terminals on the probe card by the independent external tester;
• and
• concurrently comparing the plurality of independent data output signals of each of the plurality of semiconductor integrated circuit chips by the independent external tester.

A method of testing semiconductor integrated circuit chips, the method comprising:

• coupling each of a plurality of probe contact terminals on at least one probe card to an independent external tester, the probe card having a plurality of probe needles and each of the plurality of probe contact terminals arranged thereon, wherein the probe contact terminals are direct connected to the probe needles by mechanical wirings;
• preparing a semiconductor wafer having a plurality of semiconductor integrated circuit chips arranged thereon in at least two columns and at least two rows, each of the plurality of semiconductor integrated circuit chips having a plurality of external terminals;
• coupling the plurality of probe needles on the probe card to the plurality of external terminals of each of the plurality of semiconductor integrated circuit chips arranged thereon in at least two columns and at least two rows;
• concurrently receiving a plurality of independent test signals and independent power supply for the probe card by each of the plurality of probe contact terminals from the independent external tester;
• concurrently supplying the plurality of independent test signals and the independent power supply through the plurality of probe needles on the probe card to each of the plurality of semiconductor integrated circuit chips from the probe card;
• concurrently receiving a plurality of independent data output signals of each of the plurality of semiconductor integrated circuit chips in response to the plurality of independent test signals and independent power supply through the plurality of probe needles on the probe card by the probe card;
• concurrently receiving the plurality of independent data output signals of each of the plurality of semiconductor integrated circuit chips through the plurality of probe contact terminals on the probe card by the independent external tester;
• and
• concurrently comparing electrical characteristics of the plurality of independent data output signals of each of the plurality of semiconductor integrated circuit chips by the independent external tester.

A method of testing semiconductor integrated circuit chips, the method comprising:

• coupling a plurality of probe contact terminals on at least one probe card to an independent external tester, the probe card having a plurality of probe needles and a plurality of probe contact terminals arranged thereon, wherein the probe contact terminals are direct connected to the probe needles by mechanical wirings;
• preparing a semiconductor wafer having a plurality of semiconductor integrated circuit chips arranged thereon in at least two columns and at least two rows, each of the plurality of semiconductor integrated circuit chips having a plurality of external terminals;
• coupling the plurality of probe needles on the probe card to the plurality of external terminals of each of the plurality of semiconductor integrated circuit chips, the plurality of probe needles being arranged on the probe card in at least two columns and at least two rows, the plurality of probe needles corresponding to those of the plurality of external terminals;
• concurrently receiving a plurality of independent test signals and independent power supply for the probe card by each of the plurality of probe contact terminals from the independent external tester;
• concurrently supplying the plurality of independent test signals and the independent power supply through the plurality of probe needles on the probe card to each of the plurality of semiconductor integrated circuit chips from the probe card;
• concurrently receiving a plurality of independent data output signals of each of the plurality of semiconductor integrated circuit chips in response to the plurality of independent test signals and independent power supply through the plurality of probe needles on the probe card by the probe card;
• concurrently receiving the plurality of independent data output signals of each of the plurality of semiconductor integrated circuit chips through the plurality of probe contact terminals on the probe card by the independent external tester;
• and
• concurrently comparing the plurality of independent data output signals of each of the plurality of semiconductor integrated circuit chips by the independent external tester.

A method of testing semiconductor integrated circuit formed in a semiconductor wafer, the method comprising:

• coupling a plurality of probe contact terminals on a probe card to an independent external tester, the probe card having a plurality of probe needles and a plurality of probe contact terminals arranged thereon, wherein the probe contact terminals are direct connected to the probe needles by mechanical wirings;
• preparing a semiconductor wafer having a plurality of semiconductor integrated circuit chips arranged thereon in at least two columns and at least two rows, each of the plurality of semiconductor integrated circuit chips having a plurality of external terminals;
• coupling the plurality of probe needles on the probe card to the plurality of external terminals of each of the plurality of semiconductor integrated circuit chips arranged thereon in at least two columns and at least two rows;
• concurrently receiving a plurality of independent test signals and independent power supply for the probe card by each of the plurality of probe contact terminals from the independent external tester;
• concurrently supplying a plurality of test signals and power supply voltages through the plurality of probe needles on the probe card to the external terminals on each of the plurality of semiconductor integrated circuit chips in at least two columns and at least two rows from the independent external tester;
• concurrently receiving independent data output signals from each of the plurality of semiconductor integrated circuit chips in at least two columns and at least two rows by the independent external tester through the external terminals, the probe needles and the probe contacts;
• and
• concurrently comparing electrical characteristics of the plurality of independent data output signals of each of plurality of semiconductor integrated circuit chips by the independent external tester.