# US RE40,947 E1 · Multilayer printed wiring board and its manufacturing method, and resin composition for filling through-hole > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US RE40,947 E1 - Document ID: USRE40947E1 - Status: Granted - Kind: E1 - Application number: 10/829,479 - Filed: 1990-10-12 - Granted: 2009-10-27 - Earliest claimed: 1990-10-12 - Assignees: Ibiden Co., Ltd. - Inventors: Motoo Asai; Kenichi Shimada; Kouta Noda; Takashi Kariya; Hiroshi Segawa - Web page: https://patentgrep.com/patent/USRE40947E1 ## Abstract A multilayer printed wiring board is composed of a substrate provided with through-holes, and a wiring board formed on the substrate through the interposition of an interlaminar insulating resin layer, the through-holes having a roughened internal surface and being filled with a filler, an exposed part of the filler in the through-holes being covered with a through-hole-covering conductor layer, and a viahole formed just thereabove being connected to the through-hole-covering conductor layer. Without peeling between the through-holes and the filler, this wiring board has a satisfactory connection reliability between the through-holes and the internal layer circuit and provides a high density wiring. ## Claims ### Claim 1 A multilayer printed wiring board comprising: a substrate provided with having at least one through-hole structure, the substrate having the at least one through-hole structure comprising a plated film and being filled with a filler; at least one interlaminar resin insulating layer formed thereon on the substrate; and at least one conductor circuit formed on the at least one interlaminar resin insulating layer, the at least one through-hole being filled with filler , wherein an internal a surface of the plated film of the at least one through-hole structure is roughened, and the filler comprises metal particles and one of thermosetting and thermoplastic resin resins. ### Claim 2 (depends on 1) The multilayer printed wiring board according to claim 1, wherein the substrate is a multilayer core substrate formed by laminating at least one conductor layer and at least one prepreg in alternating order. ### Claim 3 (depends on 1) The multilayer printed wiring board according to claim 1, wherein at least one through-hole structure formed on in the substrate has a pitch interval of equal to or less than 700 μm. ### Claim 4 (depends on 1) The multilayer printed wiring board according to claim 1, comprising build-up wiring layers including at least one via-hole provided in the at least one interlaminar resin insulating layer wherein the at least one interlaminar resin insulating layer comprises a plurality of interlaminar resin insulating layers, the plurality of interlaminar resin insulating layers and at least one via-hole provided in the interlaminar resin insulating layers to form build-up wiring layers, and the build-up wiring layers are formed on both surfaces of the substrate, and have the same number of layers with each other on both surfaces of the substrate. ### Claim 5 The multilayer printed wiring board comprising: a substrate provided with having at least one through-hole structure, the substrate having the at least one through-hole structure being filled with a filler; at least one interlaminar resin insulating layer formed thereon on the substrate; and at least one conductor circuit formed on the at least one interlaminar resin insulating layer, the at least one through-hole being filled with filler , wherein an internal surface of the at least one through-hole structure is roughened, and the filler comprises a particulate substance including metal particles having a particle size of from 0.1 to 30 μm, a resin, and an ultrafine inorganic powder having a particle size from 1 to 1000 2 to 100 nm. ### Claim 6 (depends on 5) The multilayer printed wiring board according to claim 5, wherein the filler is a nonconducting composition containing metal particles . ### Claim 7 (depends on 5) The multilayer printed wiring board according to claim 5, wherein the particulate substance further comprises at least one of metal particles, inorganic particles and resin particles. ### Claim 8 (depends on 5) The multilayer printed wiring board according to claim 5, wherein the resin comprises at least one of bisphenol epoxy resin and novolac epoxy resin. ### Claim 9 (depends on 5) The multilayer printed wiring board according to claim 5, wherein the substrate is a multilayer core substrate formed by laminating at least one conductor layer and at least one prepeg in alternating order. ### Claim 10 (depends on 5) The multilayer printed wiring board according to claim 5, wherein the at least one through-hole structure formed on in the substrate has a pitch interval of equal to or less than 700 μm. ### Claim 11 (depends on 5) The multilayer printed wiring board according to claim 5, comprising build-up wiring layers including at least one via-hole provided in the at least one interlaminar resin insulating layer wherein the at least one interlaminar resin insulating layer comprises a plurality of interlaminar resin insulating layers, the plurality of interlaminar resin insulating layers and at least one via-hole provided in the interlaminar resin insulating layers to form build-up wiring layers, and the build-up wiring layers are formed on both surfaces of the substrate, and have the same number of layers with each other on both surfaces of the substrate. ### Claim 12 A multilayer printed wiring board comprising: a substrate provided with having at least one through-hole structure, the substrate having the at least one through-hole structure comprising a plated film and being filled with a filler; at least one interlaminar resin insulating layer formed thereon on the substrate; and at least one conductor circuit formed on the at least one interlaminar resin insulating layer, the at least one through-hole being filled with filler , wherein an internal a surface of the plated film of the at least one through-hole structure is roughened, and the filler comprises metal particles and one of thermosetting and thermoplastic resin resins, and an exposed portion of the filler in the at least one through-hole is covered with a portion of the at least one conductor circuit through-hole-covering conductor layer. ### Claim 13 (depends on 12) The multilayer printed wiring board according to claim 12, wherein a roughened layer is formed on a surface of the at least one conductor circuit through-hole-covering conductor layer covering at least the one through-hole structure is roughened. ### Claim 14 (depends on 12) The multilayer printed wiring board according to claim 12, wherein the substrate is a multilayer core substrate formed by laminating at least one conductor layer and at least one prepreg in alternating order. ### Claim 15 (depends on 12) The multilayer printed wiring board according to claim 12, wherein the at least one through-hole structure formed on in the substrate has a pitch interval of equal to or less than 700 μm. ### Claim 16 (depends on 12) The multilayer printed wiring board according to claim 12, comprising build-up wiring layers including the at least one via-hole provided in the at least one interlaminar resin insulating layer wherein the at least one interlaminar resin insulating layer comprises a plurality of interlaminar resin insulating layers, the plurality of interlaminar resin insulating layers and at least one via-hole provided in the interlaminar resin insulating layers to form build-up wiring layers, and the build-up wiring layers are formed on both surfaces of the substrate, and have the same number of layers with each other on both surfaces of the substrate. ### Claim 17 The multilayer printed wiring board comprising: a substrate provided with having at least one through-hole structure, the substrate having the at least one through-hole structure being filled with a filler; at least one interlaminar resin insulating layer formed thereon on the substrate; and at least one conductor circuit formed on the at least one interlaminar resin insulating layer, the at least one through-hole being filled with filler , wherein an internal surface of the at least one through-hole structure is roughened, and the filler comprises a particulate substance having a particle size of from 0.1 to 30 μm, a resin, and an ultrafine inorganic powder having a particle size from 1 to 1000 2 to 100 nm, and an exposed portion of the filler in the at least one through-hole structure is covered with a portion of the at least one conductor circuit through-hole-covering conductor layer. ### Claim 18 (depends on 17) The multilayer printed wiring board according to claim 17, wherein the filler is a nonconducting composition containing metal particles. ### Claim 19 (depends on 17) The multilayer printed wiring board according to claim 17, wherein the particulate substance comprises at least one of metal particles, inorganic particles and resin particles. ### Claim 20 (depends on 17) The multilayer printed wiring board according to claim 17, wherein the resin comprises at least one of bisphenol epoxy resin and novolac epoxy resin. ### Claim 21 (depends on 17) The multilayer printed wiring board according to claim 17, wherein a roughened layer is formed on a surface of the at least one conductor circuit through-hole-covering conductor layer covering the at least one through-hole structure is roughened. ### Claim 22 (depends on 17) The multilayer printed wiring board according to claim 17, wherein the substrate is a multilayer core substrate formed by laminating at least one conductor layer and at least one prepreg in alternating order. ### Claim 23 (depends on 17) The multilayer printed wiring board according to claim 17, wherein at least one through-hole structure formed on in the substrate has a pitch interval equal to or less than 700 μm. ### Claim 24 (depends on 17) The multilayer printed wiring board according to claim 17, comprising build-up wiring layers including the at least one via-hole provided in the at least one interlaminar resin insulating layer wherein the at least one interlaminar resin insulating layer comprises a plurality of interlaminar resin insulating layers, the plurality of interlaminar resin insulating layers and at least one via-hole provided in the interlaminar resin insulating layers to form build-up wiring layers, and the build-up wiring layers are formed on both surfaces of the substrate, and have the same number of layers with each other on both surfaces of the substrate. ### Claim 25 A multilayer printed wiring board comprising: a substrate provided with having at least one through-hole structure, the substrate having the at least one through-hole structure comprising a plated film and being filled with a filler; at least one interlaminar resin insulating layer formed thereon on the substrate; and at least one conductor circuit formed on the at least one interlaminar resin insulating layer, the at least one through-hole being filled with filler , wherein an internal a surface of the plated film of the at least one through-hole structure is roughened, and the filler comprises metal particles and one of thermosetting and thermoplastic resin resins, and an exposed surface of the filler in the at least one through-hole structure is covered with a portion of the at least one conductor circuit through-hole-covering conductor layer, and at least one viahole is formed in the at least one interlaminar resin insulating layer just directly above the at least one conductor circuit and is connected to the at least one conductor circuit through-hole-covering conductor layer. ### Claim 26 (depends on 25) The multilayer printed wiring board according to claim 25, wherein a roughened layer is formed on surface of the through-hole-covering conductor layer is roughened. ### Claim 27 (depends on 25) The multilayer printed wiring board according to claim 25, wherein the substrate is a multilayer core substrate formed by laminating at least one conductor layer and at least one prepreg is alternating order. ### Claim 28 (depends on 25) The multilayer printed wiring board according to claim 25, wherein the at least one through-hole structure formed on in the substrate has a pitch interval of equal to or less than 700 μm. ### Claim 29 (depends on 25) The multilayer printed wiring board according to claim 25, comprising build-up wiring layers including the at least one via-hole provided in the at least one interlaminar resin insulating layer wherein the at least one interlaminar resin insulating layer comprises a plurality of interlaminar resin insulating layers, the plurality of interlaminar resin insulating layers and at least one via-hole provided in the interlaminar resin insulating layers to form build-up wiring layers, and the build-up wiring layers are formed on both surfaces of the substrate, and have the same number of layers with each other on both surfaces of the substrate. ### Claim 30 A multilayer printed wiring board comprising: a substrate provided with having at least one through-hole structure, the substrate having the at least one through-hole structure being filled with a filler; at least one interlaminar resin insulating layer formed thereon on the substrate; and at least one conductor circuit formed on the at least one interlaminar resin insulating layer, the at least one through-hole being filled with filler , wherein an internal surface of the at least one through-hole structure is roughened, and the filler comprises a particulate substance having a particle size of from 0.1 to 30 μm, a resin, and an ultrafine inorganic powder having a particle size from 1 to 1000 2 to 100 nm, and an exposed surface of the filler in the at least one through-hole structure is covered with a portion of the at least one conductor circuit through-hole-covering conductor layer, and at least one viahole is formed in the at least one interlaminar resin insulating layer just directly above the at least one conductor circuit and is connected to the at least one conductor circuit through-hole-covering conductor layer. ### Claim 31 (depends on 30) The multilayer printed wiring board according to claim 30, wherein the filler is a nonconducting composition containing metal particles. ### Claim 32 (depends on 30) The multilayer printed wiring board according to claim 30, wherein the particulate substance comprises at least one of metal particles, inorganic particles and resin particles. ### Claim 33 (depends on 30) The multilayer printed wiring board according to claim 30, wherein the resin comprises at least one of bisphenol epoxy resin and novolac epoxy resin. ### Claim 34 (depends on 30) The multilayer printed wiring board according to claim 30, wherein a roughened layer is formed on a surface of the at least one conductor circuit covering the at least one through-hole through-hole-covering conductor layer is roughened. ### Claim 35 (depends on 30) The multilayer printed wiring board according to claim 30, wherein the substrate is a multilayer core substrate formed by laminating at least one conductor layer and at least one prepreg in alternating order. ### Claim 36 (depends on 30) The multilayer printed wiring board according to claim 30, wherein the least one through-hole structure formed on in the substrate has a pitch interval of equal to or less than 700 μm. ### Claim 37 (depends on 30) The multilayer printed wiring board according to claim 30, comprising build-up wiring layers including the at least one via-hole provided in the at least one interlaminar resin insulating layer wherein the at least one interlaminar resin insulating layer comprises a plurality of interlaminar resin insulating layers, the plurality of interlaminar resin insulating layers and at least one via-hole provided in the interlaminar resin insulating layers to form build-up wiring layers, and the build-up wiring layers are formed on both surfaces of the substrate, and have the same number of layers with each other on both surfaces of the substrate. ### Claim 38 A resin composition for filling through-hole of a printed wiring board comprising: a particulate substance comprising metal powder particles having an average particle size ranging from 0.1 to 30 μm and being present in an amount ranging from 30 to 90% by weight of the total solids content of the resin composition, ; a resin and an ultrafine inorganic powder having an average particle size ranging from 1 to 1,000 2 to 100 nm. ### Claim 39 (depends on 38) The resin composition according to claim 38, which is a nonconducting composition. ### Claim 40 (depends on 38) The resin compositon composition according to claim 38, wherein the particulate substance further comprises at least one member selected from metal particulate, the group consisting of inorganic particles or and resin particles. ### Claim 41 (depends on 38) The resin composition according to claim 38, wherein the resin comprises at least one of bisphenol epoxy resin and novolac epoxy resin. ### Claim 42 (depends on 41) The resin composition according to claim 41, wherein the bisphenol epoxy resin comprises at least one of bisphenol P epoxy resin and bisphenol A epoxy resin. ### Claim 43 (depends on 41) The resin composition according to claim 41, wherein the novolac epoxy resin comprises at least one of phenol novolac epoxy resin and cresol novolac epoxy resin. ### Claim 44 (depends on 41) The resin composition according to claim 41, wherein the composition ratio of the novolac epoxy resin to the bisphenol epoxy resin ranges from 1/1 to 1/100 by weight. ### Claim 45 (depends on 38) The resin composition according to claim 38, wherein the ultrafine inorganic powder is present in an amount ranging from 0.1 to 5% by weight of the total solids content of the resin composition and has an average particle size ranging from 2 to 200 nm. ### Claim 46 (depends on 38) The resin composition according to claim 38, wherein the ultrafine inorganic powder is comprises at least one material selected from the group consisting of silica, alumina, silicon carbide or and mullite. ### Claim 47 (depends on 46) The resin composition according to claim 46, wherein the ultrafine inorganic powder is silica. ### Claim 48 A process of producing a multilayer printed wiring board comprising: forming a hole in a substrate; forming at least one conductor layer on both surfaces of a substrate by electroless plating, forming at least one a through-hole on structure in the substrate, by plating a layer on a surface of the hole; forming a roughened layer on an internal roughening a surface of the plated layer of the at least one through-hole structure;, filling the at least one through-hole structure including the plated layer having the a roughened layer on its internal surface with a filler comprising metal particles and one of thermosetting and thermoplastic resin, and drying and curing the filler, resins; forming a first conductor layer having a first conductor circuit on the substrate; forming at least one a first interlaminar resin insulating layer, and on the first conductor circuit and the substrate; forming an opening for a via hole in the interlaminar resin insulating layer; and forming at least one a second conductor layer having a second conductor circuit by electroless plating on the first interlaminar resin insulating layer and the via hole in the opening, wherein the via hole is formed to connect the first conductor circuit and the second conductor circuit. ### Claim 49 (depends on 48) The process according to claim 48, wherein the internal surface of the at least one plated layer of the through-hole structure is roughened by a treatment selected from the group consisting of an oxidation-reduction treatment, a treatment with an aqueous mixed solution of an organic acid and a copper (II) complex, or and a plating treatment with a needle ternary alloy of copper-nickel-phosphorous. ### Claim 50 (depends on 48) The process according to claim 48, wherein forming the least one conductor layer comprises electroplating after electroless plating. ### Claim 51 (depends on 48) The process according to claim 48, wherein forming the at least one conductor circuit first conductor circuit and the second conductor circuit comprises electroplating after electroless plating. ### Claim 52 A process of producing a multilayer printed wiring board, comprising: forming a hole in a substrate; forming at least one conductor layer on both surfaces of a substrate by electroless plating, forming at least one a through-hole through structure in the substrate, by plating a layer on a surface of the hole; forming a roughened layer on an internal roughening a surface of the plated layer of the at least one through-hole, structure; filling the at least one through-hole structure including the plated layer having the a roughened layer on its internal surface with a filler comprising a particulate substance including metal particles having a particle size of from 0.1 to 30 μm, a resin, and an ultrafine inorganic powder having a particle size from 1 to 1000 2 to 100 nm, and drying and curing the filler, ; forming a first conductor layer having a first conductor circuit on the substrate; forming at least one a first interlaminar resin insulating layer, and on the first conductor circuit and the substrate; forming an opening for a via hole in the first interlaminar resin insulating layer; and forming at least one a second conductor layer having a second conductor circuit by electroless plating on the first interlaminar resin insulating layer and the via hole in the opening, wherein the via hole is formed to connect the first conductor circuit and the second conductor circuit. ### Claim 53 (depends on 52) The process according to claim 52, wherein the filler is a nonconducting composition containing metal particles . ### Claim 54 (depends on 52) The process according to claim 52, wherein the particulate substance further comprises at least one of metal particles, inorganic particles and resin particles. ### Claim 55 (depends on 52) The process according to claim 52, wherein the resin comprises at least one of bisphenol epoxy resin and novolac epoxy resin. ### Claim 56 (depends on 52) The process according to claim 52, wherein forming the at least one first conductor layer and the second conductor layer comprises electroplating after electroless plating. ### Claim 57 (depends on 52) The process according to claim 52, wherein forming the at least one first conductor circuit and the second conductor circuit comprises electroplating after electroless plating. ### Claim 58 A process of producing a multilayer printed wiring board comprising: forming at least one conductor layer on both surfaces of a substrate by electroless plating, forming at least one through-hole on the substrate, forming a roughened layer on an internal surface of the at least one through-hole, filling the at least one through-hole having the roughened layer on its internal surface with filler comprising metal particles and one of thermosetting and thermoplastic resin, and drying and curing the filler, forming a portion of the at least one conductor layer on the at least one through-hole by subjecting a portion of the filler on the at least one through-hole to electroless plating, forming at least one interlaminar resin insulating layer, and forming at least one conductor circuit by electroless plating. ### Claim 59 (depends on 58) The process according to claim 58, wherein the internal surface of the at least one through-hole is roughened by any process selected from an oxidation-reduction treatment, a treatment with an aqueous mixed solution of an organic acid and a copper (II) complex, or a plating treatment with a needle ternary alloy of copper-nickel-phosphorus. ### Claim 60 (depends on 58) The process according to claim 58, wherein the forming the portion of the at least one conductor layer on the at least one through-hole comprises smoothing a surface of the substrate, applying catalyst nuclei to the smoothed surface of the substrate, subjecting the substrate to electroless plating to form a plating layer, forming an etching resist just above the at least one through-hole and on a portion of the at least one through-hole and the plating layer which is to become a part of the at least one conductor circuit, removing the plating layer in a portion of the substrate where the etching resist is not formed, and removing the etching resist. ### Claim 61 (depends on 60) The process according to claim 60, comprising subjecting the substrate to electroplating after electroless plating. ### Claim 62 (depends on 60) The process according to claim 60, wherein the forming the portion of the at least one conductor layer on the at least one through-hole comprises smoothing a surface of the substrate, forming a plating resist on a part of the smoothed surface of the substrate, subjecting a portion of the smoothed surface of the substrate where the resist is not formed to electroplating to form the at least one conductor layer and the at least one conductor circuit, and removing the plating resist with the at least one conductor layer located beneath the plating resist by etching. ### Claim 63 (depends on 60) The process according to claim 60, wherein the forming the portion of the at least one conductor layer on the at least one through-hole comprises roughening a surface of the portion of the at least one conductor layer by a treatment selected from oxidation-reduction treatment, treatment with an aqueous mixed solution of an organic acid and a copper (II) complex, or plating treatment with needle ternary alloy of copper-nickel-phosphorus. ### Claim 64 (depends on 60) The process according to claim 60, wherein forming the at least one conductor layer comprises electroplating after electroless plating. ### Claim 65 (depends on 60) The process according to claim 60, wherein forming the portion of the at least one conductor layer on the at least one through-hole comprises electroplating after electroless plating. ### Claim 66 A process of producing a multilayer printed wiring board comprising: forming at least one conductor layer on both surfaces of a substrate by electroless plating, forming at least one through-hole on the substrate, forming a roughened layer on an internal surface of the at least one through-hole, filling the at least one through-hole having the roughened layer on its internal surface with filler comprising particulate substance having a particle size of from 0.1 to 30 μm, resin, and ultrafine inorganic powder having a particle size from 1 to 1000 nm, and drying and curing the filler, forming a portion of the at least one conductor layer on the at least one through-hole by subjecting a portion of the filler on the at least one through-hole to electroless plating, forming at least one interlaminar resin insulating layer, and forming at least one conductor circuit by electroless plating. ### Claim 67 (depends on 66) The process according to claim 66 52, wherein the filler is a nonconducting composition having a specific resistance of equal to or more than 1×106 Ω·cm2 and containing metal particles Ω·cm. ### Claim 68 (depends on 67) The process according to claim 67, wherein the particulate substance further comprises at least one of metal particles, inorganic particles and resin particles. ### Claim 69 (depends on 67) The process according to claim 67, wherein the resin comprises at least one of bisphenol epoxy resin and novolac epoxy resin. ### Claim 70 (depends on 66) The process according to claim 66, wherein forming the at least one conductor layer comprises electroplating after electroless plating. ### Claim 71 (depends on 66) The process according to claim 66 52, wherein forming the portion of the at least one conductor layer on the at least one through-hole comprises wherein the forming of the first conductor layer includes subjecting a portion of the filler in the through-hole to electroless plating and electroplating after electroless plating to cover the through-hole. ### Claim 72 A process of producing a multilayer printed wiring board comprising: forming a hole in a substrate; forming at least one conductor layer on both surfaces of a substrate by electroless plating, forming at least one a through-hole on structure in the substrate, by plating a layer on a surface of the hole; forming a roughened layer on an internal roughening a surface of the plated layer of the at least one through-hole, structure; filling the at least one through-hole structure including the plated layer having the a roughened layer on its internal surface with a filler comprising metal particles and one of the thermosetting and thermoplastic resin, and drying and curing the filler, resins; forming a portion of the at least one first conductor layer having a through-hole-covering conductor layer on the at least one through-hole by subjecting a portion of the filler on the at least one through-hole to electroless plating, structure; forming at least one a first interlaminar resin insulating layer, on the first conductor layer; and forming at least one viahole in the first interlaminar resin insulating layer and at least one a second conductor circuit in on the at least one first interlaminar resin insulating layer located just above the at least one through-hole, and , wherein the at least one viahole is formed at a position directly above the through-hole structure and provided to connect the through-hole-covering conductor layer with the second conductor circuit connecting the at least one viahole to the at least one conductor circuit in the at least one interlaminar resin insulating layer located just above the at least one through-hole . ### Claim 73 (depends on 72) The process according to claim 72, wherein the internal surface of the at least one plated layer of the through-hole structure is roughened by a treatment selected from the group consisting of oxidation-reduction treatment, treatment with an aqueous mixed solution of an organic acid and a copper (II) complex, or and plating treatment with needle ternary alloy of copper-nickel-phosphorus. ### Claim 74 (depends on 72) The process according to claim 72, wherein the forming the portion of the at least one conductor layer through-hole-covering conductor layer on the at least one through-hole structure comprises smoothing a surface of the substrate, applying catalyst nuclei to the smoothed surface of the substrate, subjecting the substrate to electroless plating to form a plating layer, subjecting the substrate to electroplating, forming an etching resist just directly above the at least one through-hole structure and on a portion of the at least one through-hole and the plating layer which is to become a part of the at least one conductor circuit structure, removing the plating layer in a portion of the substrate where the etching resist is not formed, and removing the etching resist. ### Claim 75 (depends on 72) The process according to claim 72, wherein the forming the portion of the at least one conductor layer through-hole-covering conductor layer on the at least one through-hole structure comprises smoothing a surface of the substrate, subjecting the substrate to electroless plating to form a plating layer, forming a plating resist on a part of the smoothed surface of the substrate the plating layer, subjecting a portion of the smoothed surface of the substrate to where the resist is not formed to electroplating to form the at least one conductor layer and the at least one conductor circuit electroplating, and removing the plating resist with , and etching the at least one conductor layer plating layer located beneath the plating resist by etching to form the through-hole-covering conductor layer. ### Claim 76 (depends on 72) The process according to claim 72, wherein the forming the portion of the at least one conductor layer through-hole-covering conductor layer on the at least one through-hole structure comprises roughening a surface of the portion of the at least one conductor layer through-hole-covering conductor layer by a treatment selected from the group consisting of oxidation-reduction treatment, treatment with an aqueous mixed solution of an organic acid and a copper (II) complex, or and plating treatment with needle ternary alloy of copper-nickel-phosphorus. ### Claim 77 (depends on 72) The process according to claim 72, wherein the at least one viahole is formed just above the at least one through-hole through the interposition of the at least one interlaminar resin insulating layer by roughening the at least one interlaminar resin insulating layer provided with an opening for the at least one viahole, applying catalyst nuclei directly to the roughened interlaminar resin insulating layer, subjecting the roughened interlaminar resin insulating layer to electroless plating, and etching the plated layer so as to leave the at least one viahole and the at least one conductor circuit portion. ### Claim 78 (depends on 72) The process according to claim 72, wherein the at least one viahole is formed just above the at least one through-hole through the interposition of the at least one interlaminar resin insulating layer by applying catalyst nuclei directly to the interlaminar resin insulating layer without roughening, subjecting the interlaminar resin insulating layer to electroless plating, and etching the plated layer so as to leave at least one viahole and the at least one conductor circuit portion. ### Claim 79 (depends on 72) The process according to claim 72, wherein forming at least one the first conductor layer on both surfaces of a the substrate comprises electroplating after electroless plating. ### Claim 80 (depends on 72) The process according to claim 72, wherein forming a portion of the at least one conductor layer through-hole-covering conductor layer on the at least one through-hole structure comprises electroplating after electroless plating. ### Claim 81 A process of producing a multilayer printed wiring board comprising: forming a hole in a substrate; forming at least one conductor layer on both surfaces of a substrate by electroless plating, forming at least one a through-hole on structure in the substrate, by plating a layer on a surface of the hole; forming a roughened layer on an internal roughening a surface of a plated layer of the at least one through-hole structure, filling the at least one through-hole structure including the plated layer having the a roughened layer on its internal surface with a filler comprising a particulate substance having a particle size of from 0.1 to 30 μm, a resin, and an ultrafine inorganic powder having a particle size from 1 to 1000 2 to 100 nm, and drying and curing the filler, ; forming a portion of the at least one first conductor layer having a through-hole-covering conductor layer on the at least one through-hole by subjecting a portion of the filler on the at least one through-hole to electroless plating, structure; forming at least one a first interlaminar resin insulating layer, ; and forming at least one viahole in the first interlaminar resin insulating layer and at least one a second conductor circuit in on the at least one first interlaminar resin insulating layer located just above the at least one through-hole, and , wherein the viahole is formed at a position directly above the through-hole structure and provided to connect the through-hole-covering conductor layer with the second conductor circuit connecting the at least one viahole to the at least one conductor circuit located just above the at least one through-hole . ### Claim 82 (depends on 81) The process according to claim 81, wherein the filler is a nonconducting composition and further the particulate substance comprises metal particles. ### Claim 83 (depends on 82) The process according to claim 82 81, wherein the particulate substance comprises at least one of metal particles, inorganic particles and resin particles. ### Claim 84 (depends on 82) The process according to claim 82, wherein the resin comprises at least one of bisphenol epoxy resin and novolac epoxy resin. ### Claim 85 (depends on 82) The process according to claim 82, wherein forming the at least one first conductor layer comprises electroplating after electroless plating. ### Claim 86 (depends on 82) The process according to claim 82, wherein forming the portion of the at least one first conductor layer on the at least one through-hole structure comprises electroplating after electroless plating. ### Claim 87 A multilayer printed wiring board comprising: a substrate having a through-hole structure comprising a plating layer and a filler provided in the through-hole structure, the plating layer having a roughened portion; a first conductor layer having a first conductor circuit formed on the substrate and a through-hole-covering conductor layer covering the filler provided in the through-hole structure having the plating layer; a first interlaminar resin insulating layer having a via hole and being formed on the substrate and the first conductor layer; and a second conductor layer having a second conductor circuit formed on the first interlaminar resin insulating layer, the second conductor circuit being connected to the first conductor circuit by the via hole. ### Claim 88 (depends on 87) The multilayer printed wiring board according to claim 87, wherein said via hole is plated with a plated film or filled with a filler. ### Claim 89 (depends on 87) The multilayer printed wiring board according to claim 87, wherein a surface of said through-hole-covering conductor layer is roughened. ### Claim 90 (depends on 89) The multilayer printed wiring board according to claim 89, wherein a side face of said through-hole-covering conductor layer is roughened. ### Claim 91 (depends on 87) The multilayer printed wiring board according to claim 87, wherein the roughened portion of the plating layer forms a roughened internal surface, and the plating layer has a thickness of at least 0.1 μm and at most 10 μm. ### Claim 92 (depends on 87) The multilayer printed wiring board according to claim 87, wherein said substrate comprises a glass-epoxy substrate, a polymide substrate, a bismaleimide-triazine resin substrate, a fluororesin substrate, a copper-clad laminate resin substrate, a ceramic substrate, or a metal substrate. ### Claim 93 (depends on 1) The multilayer printed wiring board according to claim 1, wherein the filler is non-conductive. ### Claim 94 (depends on 12) The multilayer printed wiring board according to claim 12, wherein the filler is non-conductive. ### Claim 95 (depends on 25) The multilayer printed wiring board according to claim 25, wherein the filler is non-conductive. ### Claim 96 (depends on 48) The process according to claim 48, wherein the forming of the first conductor layer comprises forming a through-hole-covering conductor layer which covers the filler. ### Claim 97 (depends on 96) The process according to claim 96, wherein the via hole is formed on the through-hole-covering conductor layer and located directly over the filler. ### Claim 98 (depends on 48) The process according to claim 48, wherein the filler is a nonconductive composition. ### Claim 99 (depends on 48) The process according to claim 48, wherein the substrate comprises copper-clad laminate, and the filler protruded from the through-hole structure is removed by polishing. ### Claim 100 (depends on 48) The process according to claim 48, wherein the forming of the first conductor layer comprises forming a through-hole-covering conductor layer to cover the filler, and the forming of the through-hole-covering conductor layer comprises performing electroless plating and electroplating after the electroless plating. ### Claim 101 (depends on 52) The process according to claim 52, wherein the forming of the first conductor layer includes forming a through-hole-covering conductor layer which covers the filler. ### Claim 102 (depends on 101) The process according to claim 101, wherein the via hole is formed on the through-hole-covering conductor layer and located directly over the filler. ### Claim 103 (depends on 52) The process according to claim 52, wherein the substrate is copper-clad laminate and the filler protruded from the through-hole structure is removed by polishing. ### Claim 104 (depends on 52) The process according to claim 52, wherein the forming of the first conductor layer includes forming a through-hole-conductor layer which covers the filler, and the forming of the through-hole-conductor layer includes performing electroless plating and electroplating after the electroless plating. ### Claim 105 (depends on 87) The multilayer printed wiring board according to claim 87, wherein the via hole is formed on the through-hole-covering conductor layer. ### Claim 106 (depends on 87) The multilayer printed wiring board according to claim 87, wherein the via hole is formed on the through-hole-covering conductor layer, and the via hole is formed above the filler. ### Claim 107 (depends on 87) The multilayer printed wiring board according to claim 87, wherein the through-hole-covering conductor layer comprises an electroless plating film and an electroplating film on the electroless plating film. ### Claim 108 (depends on 87) The multilayer printed wiring board according to claim 87, wherein the filler comprises metal particles. ### Claim 109 (depends on 108) The multilayer printed wiring board according to claim 108, wherein the filler is non-conductive. ### Claim 110 A process of producing a multilayer printed wiring board comprising: forming a hole in a substrate; forming a through-hole structure in the substrate by plating a layer on a surface of the hole; roughening a portion of the plating layer of the through-hole structure; filling a filler inside the through-hole structure; forming a first conductor layer having a first conductor circuit on the substrate and a through-hole-covering conductor layer covering the filler; forming a first interlaminar resin insulating layer on the first conductor layer and substrate; forming an opening for a via hole in the interlaminar resin insulating layer; and forming a second conductor layer having a second conductor circuit on the first interlaminar resin insulating layer and the via hole in the opening, wherein the via hole is formed to connect the first conductor circuit and the second conductor circuit. ### Claim 111 (depends on 110) The process according to claim 110, wherein the via hole is formed on the through-hole-covering conductor layer at a position directly above the filler. ### Claim 112 (depends on 110) The process according to claim 110, wherein the filler comprises metal particles and one of thermosetting and thermoplastic resins.