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US RE40,939 E1Granted
Multi-phase locked loop for data recovery
AssigneeRealtek Semiconductor Corp.
InventorChen-Chih Huang
Life of this patent
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Abstract
The present invention provides a multi-phase-locked loop without dead zone, which can reduce clock jitter and provide larger tolerance for data random jitter. It generates and output multiple sets of control signals (upk/dnk) via a multi-phase voltage controlled oscillator which generates a plurality of multi-phase clock signals for detecting the transition edge of data signal. Therefore, the phase error θe and the voltage Vd of the multi-phase-locked loop can be adjusted to be nearly linear according to the control signals. A multi-phase-locked loop without dead zone thus can be provided.
Claims19
A multi-phase-locked loop for data recovery comprising a phase detector, a charge pump, a loop filter and a voltage controlled oscillator, wherein:
- said phase detector is constituted by N phase detection units (U1, U2, . . . , UN, N is even, N≧4);
- said N phase detection units are connected in cascade configuration, and each phase detection unit contains:
- a data signal input terminal for receiving a data signal from outside;
- a clock signal input terminal for receiving the one of multi-phase clock signals (CK1, CK2, . . . , CKN) from outside;
- a delay signal input terminal for receiving a delay signal output from another phase detection unit;
- a delay signal output terminal for outputting a delay signal of the phase detection unit;
- and
- a charge/discharge control signal output terminal for outputting a control signals for charge/discharge operations;
- each of said N phase detection units generates a delay signal (D1, D2, . . . , DN) according to an input the data signal and the complement of a the multi-phase clock signal;
- the delay signal (Dj+1) generated by the (j+1)th phase detection unit is input into the jth phase detection unit via the jth delay signal input terminal;
- the delay signal (D1) generated by the first phase detection unit is input into the Nth phase detection unit via the Nth delay signal input terminal;
- the jth phase detection unit (Uj′ Uj, 1≦j<N, j is a positive integer) generates one of the control signals (dn1, dn2, . . . , dnN/2, upN/2, . . . , up2) for charge/discharge operations according to the delay signal (Dj) from the jth phase detection unit, the delay signal (Dj+1) from the (j+1)th phase detection unit, and the multi-phase clock signal (CKj) which is applied to the jth phase detection unit;
- the Nth phase detection unit generates a charge control signal (up1) according to the delay signal (Dn) from the Nth phase detection unit, the delay signal (D1) from the first phase detection unit, and the multi-phase clock signal (CKN) which is applied to the Nth phase detection unit;
- said charge pump being constituted by N/2 charge and discharge units (CP1, CP2, . . . , CPN/2), wherein the kth (CPk, 1≦k≦N/2) charge and discharge unit (CPk) is employed to receive the kth charge/discharge control signal set (upk/dnk) from said phase detector, and a current Ichk is generated by the charge/discharge control signal set (upk/dnk);
- the charge/discharge current Ichk=(wk×upk−wk×dnk)Iss, wherein wk is a weighting value, Iss is a fixed current value, and w1<w2< . . . <wN/2;
- the total charge/discharge current (Ich) from said charge pump equals to Ich1+Ich2+ . . . Ichk+ . . . +IchN/2;
- and
- said voltage controlled oscillator is a multi-phase voltage controlled oscillator, which outputs N multi-phase clock signals (CK1, CK2 . . . , CKN), which are applied to said phase detectors phase detection units, respectively.
15 more elements
A multi-phase-locked loop comprising:
- a phase detector configured to:
- receive a data signal and a plurality of multi-phase clock signals;
- detect a phase difference between the data signal and each multi-phase clock signal;
- and
- output a plurality of control signals;
- a charge pump, configured to receive the control signals and produce a total control current according to the control signals, the charge pump comprising a plurality of charge/discharge units, wherein at least one of charge/discharge units comprises a first current source, a second current source, and a switch module, and wherein each charge/discharge unit has a weighting value, and at least two of the weighting values are different;
- a loop filter configured to receive the total control current and produce a control voltage according to the total control current;
- and
- a voltage controlled oscillator (VCO) configured to produce the multi-phase clock signals according to the control voltage, wherein the multi-phase clock signals are at substantially the same frequency.
6 more elements
A multi-phase-locked loop comprising:
- a phase detector configured to:
- receive a data signal and a plurality of multi-phase clock signals;
- detect a phase different between the data signal and each multi-phase clock signal;
- and
- output a plurality of control signals;
- a charge pump, configured to receive the control signals and produce a total control current according to the control signals;
- said charge pump including a first current source, a second current source, and a switch module;
- a loop filter configured to receive the total control current and produce a control voltage according to the total control current;
- and
- a voltage controlled oscillator (VCO) configured to produce the multi-phase clock signals according to the control voltage, wherein the multi-phase clock signals are at substantially the same frequency, wherein the phase detector comprises N phase detection units (N is even, N>=4), the N phase detection units being coupled in cascade configuration.
7 more elements
A phase detector for detecting phase differences between a data signal and a plurality of multi-phase clock signals and producing a plurality of control signals, wherein the frequencies of the multi-phase clock signals are substantially the same, the phase detector comprising:
- a plurality of phase detection units, the phase detection units being coupled in cascade configuration, wherein each of the phase detection units comprises:
- a first flip-flop configured to generate a delay signal according to the corresponding multi-phase clock signal and the data signal;
- an exclusive OR gate configured to receive the delay signal from the first flip-flop and another delay signal from another first flip-flop in another phase detection unit;
- and
- a second flip-flop configured to generate one of the plurality of control signals according to an output signal of the exclusive OR gate and the corresponding multi-phase clock signal.
2 more elements
The multi-phase-locked loop, comprising:
- a phase detector configured to:
- receive a data signal and a plurality of multi-phase clock signals;
- detect a phase difference between the data signal and each multi-phase clock signal;
- and
- output a plurality of control signals;
- a charge pump, configured to receive the control signals and produce a total control current according to the control signals;
- a loop filter configured to receive the total control current and produce a control voltage according to the total control current;
- and
- a voltage controlled oscillator (VCO) configured to produce the multi-phase clock signals according to the control voltage, wherein the multi-phase clock signals are at substantially the same frequency;
- wherein the charge pump comprises a plurality of charge/discharge units, each charge/discharge unit has a corresponding weighting value, and at least two of the weighting values are different.
7 more elements
Dependencies are inferred from the claim text.