Content addressable memory (CAM) devices that perform pipelined multi-cycle look-up operations using cam sub-arrays and longest match detection

A content addressable memory (CAM) system comprising:

• an input circuit configured to provide a first key and a second key, wherein the first and second keys include sequential, non-overlapping sub-fields of an input data value;
• a first CAM sub-array having a plurality of rows of CAM cells, the first CAM sub-array being coupled to receive the first key, and in response, generate a first match signal that identifies each of the rows in the first CAM sub-array that matches the first key;
• and
• a second CAM sub-array having a plurality of rows of CAM cells, the second CAM sub-array being coupled to receive the second key, and in response, generate a second match signal that identifies each of the rows in the second CAM sub-array that matches the first key and the second key.

A content addressable memory (CAM) system comprising:

• a splitter circuit configured to divide an input data value into a plurality of non-overlapping key values;
• a plurality of CAM sub-arrays arranged in a row-column configuration, each of the CAM sub-arrays being configured to receive a corresponding one of the key values, and in response, provide a match signal, wherein each of the CAM sub-arrays includes match logic for selectively enabling and disabling individual rows of the CAM sub-arrays, the match signal from each of the CAM sub-arrays being coupled to the match logic of a subsequent adjacent CAM sub-array;
• a plurality of selectors wherein each selector is coupled to receive a match signal from a corresponding CAM sub-array and a match signal from a previous CAM sub-array;
• and
• a plurality of decoders, each being coupled to receive a match signal from a corresponding CAM sub-array and provide a control signal to a corresponding selector, wherein each control signal indicates whether the corresponding match signal is representative of a no-match condition.

A content addressable memory (CAM) system comprising:

• a splitter circuit configured to divide an input data value into a plurality of non-overlapping key values;
• a plurality of CAM sub-arrays arranged in a row-column configuration, each of the CAM sub-arrays being configured to receive a corresponding one of the key values, and in response, provide a match signal, wherein each of the CAM sub-arrays includes match logic for selectively enabling and disabling individual rows of the CAM sub-arrays, the match signal from each of the CAM sub-arrays being coupled to the match logic of a subsequent adjacent CAM sub-array;
• means for routing a match signal representative of a longest match;
• and
• a priority encoder coupled to receive the match signal representative of the longest match from the means for routing.

A method of operating a content addressable memory (CAM) system including a CAM array arranged in a row-column formation, the method comprising the steps of:

• generating a first key and a second key from an input data value, the first key comprising one or more consecutive bits of the input data value, and the second key comprising one or more consecutive bits of the input data value that adjoin the bits of the first key;
• comparing the first key with data stored in each row of a first CAM sub-array, the first CAM sub-array comprising columns of the CAM array corresponding to the bits of the first key;
• generating a first match signal that identifies rows of the first CAM sub-array that match the first key;
• comparing the second key with the data stored in rows of a second CAM sub-array, wherein rows in the second CAM sub-array are enabled and disabled in response to the first match signal, the second CAM sub-array comprising columns of the CAM array corresponding to the bits of the second key;
• and
• generating a second match signal that identifies rows of the second CAM sub-array that match the second key.

A content addressable memory (CAM) system, comprising:

• an input circuit configured to receive an input data value and divide the input data value into a series of keys;
• and
• a CAM array configured to receive the series of keys and perform successive comparison operations between the series of keys and rows of data bit values stored within said CAM array, said CAM array comprising:
• a first CAM sub-array configured to compare a first of the series of keys to rows of data bit values stored within the first CAM sub-array and generate a first set of match signals;
• and
• a second CAM sub-array responsive to the first set of match signals, said second CAM sub-array configured to compare a second of the series of keys to rows of data bit values stored within the second CAM sub-array that are enabled by the first set of match signals and generate a second set of match signals.