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US RE40,894 E1Granted
Sample and load scheme for observability internal nodes in a PLD
AssigneeAltera Corporation
InventorsRakesh H. Patel, Kevin A. Norman
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Abstract
A programmable logic device (PLD) that provides the capability to observe and control the logic state of buried internal nodes is disclosed. The PLD provides shadow storage units for internal nodes such as logic element registers, memory cells, and I/O registers. A sample/load data path includes bidirectional data buses and shift register that facilitate the sampling of internal nodes for observing their logic states, and loading of internal nodes for controlling their logic states.
Claims52
In a programmable logic device (PLD), an input/output (I/O) architecture comprising:
- a plurality of I/O cells disposed along a periphery of the PLD and coupled to respective I/O terminals, each I/O cell having an I/O register;
- and
- a plurality of shadow I/O storage units corresponding, and respectively coupled, to said plurality of I/O registers,
- wherein, in an observable mode, data is selectively sampled from an I/O register in an I/O cell into a respective shadow I/O storage unit, and made available on an I/O terminal.
1 more element
A programmable logic device (PLD) with observable and controllable internal nodes, said PLD comprising:
- a plurality of logic elements coupled by an interconnect network, each logic element comprising a primary register coupled to a shadow storage unit;
- a memory array having a plurality of primary memory cells respectively coupled to a corresponding plurality of shadow storage units;
- and
- a plurality of input/output (I/O) cells respectively coupled to a corresponding plurality of I/O terminals, each I/O cell comprising a primary I/O register coupled to a shadow storage unit,
- wherein, in an observe mode of operation, data is selectively sampled from said primary register, primary memory cell and primary I/O register into their respective shadow storage units and made available on PLD I/O terminal, and
- wherein, in a load mode of operation, data is selectively loaded from shadow storage units into respective primary register, memory cell and I/O register.
3 more elements
A method for observing and controlling the logic state of internal nodes of a probable programmable logic device (PLD), said method comprising the steps of:
- A. providing a shadow storage unit for each internal node whose logic state is to be observed and controlled;
- B. coupling said shadow storage unit to its respective internal node by a selective coupling circuit;
- C. providing a data path from PLD input/output terminals to said shadow storage unit;
- and
- D. observing a logic state of an internal node by:
- i. transferring a logic state of said internal node into its respective shadow storage unit in a sample mode, and
- ii. transferring said logic state from said shadow storage unit to a PLD I/O terminal via said data path in an observe mode.
4 more elements
A method of determining the contents of a memory block in a programmable logic device, the method comprising:
- in the memory block, providing a plurality of memory storage cells and a corresponding plurality of shadow cells;
- writing data to at least one of the plurality of memory storage cells;
- storing data in the plurality of memory storage cells;
- transferring the data stored in the plurality of memory storage cells to the corresponding plurality of shadow cells;
- storing the transferred data in the plurality of shadow cells;
- and
- reading the data stored in the plurality of shadow cells,
- wherein the transferring of the data is done by a corresponding plurality of transfer circuits, and
- wherein each of the plurality of memory storage cells comprises a first inverter and a second inverter, an input of the first inverter coupled to an output of the second inverter, an output of the first inverter coupled to an input of the second inverter, and wherein each shadow cell comprises a third inverter and a fourth inverter, an input of the third inverter coupled to an output of the fourth inverter, an output of the third inverter coupled to an input of the fourth inverter.
6 more elements
A method of initializing a memory block in a programmable logic device, the method comprising:
- in the memory block, providing a plurality of shadow cells and a corresponding plurality of memory storage cells;
- writing data to at least one of the plurality of shadow cells;
- storing data in the plurality of shadow cells;
- transferring the data stored in the plurality of shadow cells to the corresponding plurality of memory storage cells;
- and
- storing the transferred data in the plurality of memory storage cells,
- wherein the transferring of the data is done by a corresponding plurality of transfer circuits, and
- wherein each of the plurality of memory storage cells comprises a first inverter and a second inverter, an input of the first inverter coupled to an output of the second inverter, an output of the first inverter coupled to an input of the second inverter, and wherein each shadow cell comprises a third inverter and a fourth inverter, an input of the third inverter coupled to an output of the fourth inverter, an output of the third inverter coupled to an input of the fourth inverter.
5 more elements
A programmable logic device comprising:
- a logic element, programmably configurable to implement user-defined combinatorial or registered logic functions;
- and
- a memory block to store data, programmably coupled to the logic element, wherein the memory block comprises a plurality of memory cells, each memory cell comprising:
- a memory storage cell to store a first data bit;
- a shadow cell to store a second data bit;
- and
- a transfer circuit, wherein when a first control line of the transfer circuit is asserted the second bit is transferred from the shadow cell to the memory storage cell, and when a second control line of the transfer circuit is asserted the first bit is transferred from the memory storage cell to the shadow cell.
4 more elements
A programmable logic device comprising:
- a logic element, programmably configurable to implement user-defined combinatorial or registered logic functions;
- and
- a memory block to store data, programmably coupled to the logic element, wherein the memory block comprises:
- a pass device;
- a memory storage cell to store data coupled to the pass device;
- a transfer circuit coupled to the memory storage cell;
- a shadow cell to store data coupled to the transfer circuit;
- and
- a inverter coupled to the shadow cell,
- wherein the transfer circuit selectively transfers data from the memory storage cell to the shadow cell or from the shadow cell to the memory storage cell, and
- wherein data is transferred from the shadow cell to the memory cell under control of a first control line, and data is transferred from the memory storage cell to the shadow cell under control of a second control line.
8 more elements
An integrated circuit comprising:
- a memory storage cell;
- a shadow cell;
- a first transfer device coupled between a first write data port line and the memory storage cell;
- a second transfer device coupled between a first read data port line and the memory storage cell;
- a third transfer device coupled between a first shadow data line and the shadow cell;
- a first device coupled between the shadow cell and a first node;
- and
- a second device coupled between the first node and a fixed voltage potential, wherein a control electrode of the second device is coupled to the memory storage cell.
5 more elements
An integrated circuit comprising:
- a memory storage cell;
- a shadow cell;
- a first transfer device coupled between a first write data port line and the memory storage cell;
- a second transfer device coupled between a first read data port line and the memory storage cell;
- a third transfer device coupled between a first shadow data line and the shadow cell;
- a first device coupled between the memory storage cell and a first node;
- and
- a second device coupled between the first node and a fixed voltage potential, wherein a control electrode of the second device is coupled to the shadow cell.
5 more elements
The memory cell of claim 44 wherein the first data line and the second data line are different lines.
A memory cell comprising:
- a first storage cell;
- a first transfer device coupled between a first data line and the first storage cell;
- a second storage cell;
- a second transfer device coupled between a second data line and the second storage cell;
- and
- a plurality of devices coupled in series between the first storage cell and a fixed voltage potential, the plurality of devices comprising:
- a first device;
- and
- a second device coupled to the first device, wherein a control electrode of the second device is coupled to the second storage cell,
- wherein data placed at the second data line cannot be transferred directly to the first storage cell without passing through the second storage cell.
7 more elements
Dependencies are inferred from the claim text.