Semiconductor chip with redistribution metal layer
AssigneesMegica Corporation, Etron Technology, Inc.
InventorsMou-Shiung Lin, Tah-Kang Joseph Ting
Life of this patent
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Abstract
A new method is provided for the creation of Input/Output connection points to a semiconductor device package. An extension is applied to the conventional I/O connect points of a semiconductor device, allowing the original I/O point location to be relocated to a new point of I/O interconnect that may be in the vicinity of the original point of I/O interconnect but can also be located at a distance from this original point of I/O interconnect. Layers of passivation and polyimide are provided for proper creation and protection of the extended and relocated I/O pads. Wire bonding is used to further interconnect the relocated I/O pads.
Claims43
A method of I/O pad relocation that provides a universal I/O pad interface allowing use of a standardized package for packaging of semiconductor devices, the relocated I/O pads being created on the surface of a thick, soft dielectric material such as polyimide, whereby the relocated I/O pads are wide metal pads, comprising the steps of:
- providing a semiconductor surface whereby said semiconductor surface has been provided with points of electrical contact therein;
- creating a base layer of SiO2 over said semiconductor surface;
- depositing a first layer of conductive material over said semiconductor surface;
- patterning and etching said first layer of conductive material, creating conductive pads that align with said points of electrical contact provided in said semiconductor surface, providing a conductive interface between said points of electrical contact provided in said semiconductor surface and said patterned and etched second layer of conductive material;
- patterning and etching said base layer of SiO2 as an extension of said patterning and etching said first layer of conductive material, using a pattern for this patterning of said base layer that is identical to a pattern used for etching said first layer of conductive material thereby removing said base layer from said semiconductor surface except where said base layer underlies said patterned first layer of conductive material;
- attaching at least one bond wire to said conductive pads for further interconnects;
- depositing a layer of passivation over said semiconductor surface, including said points of electrical contact;
- patterning and etching said layer of passivation, creating openings in said layer of passivation to said points of electrical contact provided in said semiconductor surface;
- depositing a first layer of dielectric comprising polyimide or photosensitive polyimide deposited to a thickness between about 5,000 and 10,000 Angstrom over said layer of passivation, including said openings created in said layer of passivation;
- patterning and etching said first layer of dielectric, creating openings in said first layer of dielectric that align with said openings in said layer of passivation;
- depositing a second layer of conductive material over the surface of said first layer of dielectric, including said openings in said first layer of dielectric;
- patterning and etching said second layer of conductive material, creating a pattern of conductive material that is wide and that serves as a bond pad;
- and
- providing a wire bond connection to said bond pad for further interconnect.
A method of I/O pad relocation that provides a universal I/O pad interface allowing use of a standardized package for packaging of semiconductor devices, the relocated I/O pads being created on the surface of a thick, soft dielectric material such as polyimide, whereby the relocated I/O pads are wide metal pads, said method comprising the steps of:
- providing a semiconductor surface whereby said semiconductor surface has been provided with points of electrical contact therein;
- creating base layer of SiO2 over said semiconductor surface;
- depositing a first layer of conductive material over said semiconductor surface;
- patterning and etching said first layer of conductive material, creating a first pattern of conductive pads that align with said points of electrical contact provided in said semiconductor surface;
- patterning and etching said base layer of SiO2 as an extension of said patterning and etching said first layer of conductive material, using a pattern for this patterning of said base layer that is identical to a pattern used for etching said first layer of conductive material thereby removing said base layer from said semiconductor surface except where said base layer underlies said patterned first layer of conductive material;
- depositing a layer of passivation over said semiconductor surface, including said first pattern of conductive pads;
- patterning and etching said layer of passivation, creating openings to said first pattern of conductive pads;
- depositing a first layer of dielectric comprising polyimide or photosensitive polyimide deposited to a thickness between about 5,000 and 10,000 Angstrom over said layer of passivation, including said openings created in said layer of passivation;
- patterning and etching said first layer of dielectric, creating openings in said first layer of dielectric that align with said openings in said layer of passivation;
- depositing a second layer of conductive material over the surface of said first layer of dielectric, including said openings in said first layer of dielectric;
- and
- patterning and etching said second layer of conductive material, creating a second pattern of conductive pads that align with said first pattern of conductive pads, creating a pattern of conductive material that is wide and that serves as bond pad;
- providing at least one bond wire to said bond pad for further interconnect.
A structure for I/O pad relocation that provides a universal I/O pad interface allowing use of a standardized package for packaging of semiconductor devices, the relocated I/O pads being located on the surface of a thick, soft dielectric material such as polyimide, whereby the relocated I/O pads are wide metal pads, said structure comprising:
- a semiconductor surface whereby said semiconductor surface has been provided with points of electrical contact therein;
- a base layer of SiO2 created over said semiconductor surface;
- a patterned and etched first layer of conductive material deposited over said semiconductor surface;
- conductive pads that align with said points of electrical contact provided in said semiconductor surface, created by patterning and etching said first layer of conductive material, providing a conductive interface between said points of electrical contact provided in said semiconductor surface and said patterned and etched second layer of conductive material;
- said base layer of SiO2 having been patterned and etched as an extension of said patterning and etching said first layer of conductive material, using a pattern for this patterning of said base layer that is identical to a pattern used for etching said first layer of conductive material thereby removing said base layer from said semiconductor surface except where said base layer underlies said patterned first layer of conductive material;
- a layer of passivation deposited over said semiconductor surface, including said points of electrical contact;
- openings in said layer of passivation to said points of electrical contact provided in said semiconductor surface, said openings created by patterning and etching said layer of passivation;
- a first layer of dielectric comprising polyimide or photosensitive polyimide deposited to a thickness between about 5,000 and 10,000 Angstrom deposited over said layer of passivation, including said openings created in said layer of passivation;
- openings in said first layer of dielectric that align with said openings in said layer of passivation, created by patterning and etching said first layer of dielectric;
- a second layer of conductive material deposited over the surface of said first layer of dielectric, including said openings in said first layer of dielectric;
- a pattern of interconnect lines and contact pads created by patterning and etching said second layer of conductive material;
- and
- at least one bond wire connected to said contact pads for further interconnect.
A chip package comprising:
- a semiconductor chip having a first edge and a second edge opposite to each other, comprising:
- a passivation layer;
- a first contact pad exposed by an opening in said passivation layer, wherein the minimum distance between said first edge and said first contact pad is small than that between said second edge and said first contact pad;
- a second contact pad connected to a top surface of said first contact pad, wherein the minimum distance between said first edge and said second contact pad is greater than that between said second edge and said second contact pad;
- a third contact pad;
- and
- a wirebonded wire connecting said second and third contact pads across said second edge.
Dependencies are inferred from the claim text.