Evaluation TEG for semiconductor device and method of evaluation
AssigneeOki Electric Industry Co., Ltd.
InventorHirokazu Hayashi
Life of this patent
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Abstract
An evaluation TEG for evaluating a semiconductor device including an SOI structure and a LOCOS having a birdbeak portion comprises two electrodes 10 and 20 having different electrode widths sufficiently large to disregard the length of the LOCOS birdbeak portion and an electrode 30 having an extremely small width substantially equal to the length of the birdbeak portion. All the electrode have the same length and are connected to test pads 10a, 20a, and 30a, respectively. The capacitance of a parasitic transistor is easily extracted by using the evaluation TEG and the evaluation of parameters causing the hump characteristics is become possible.
Claims17
A method of evaluating a semiconductor device including a substrate, a dielectric layer, and an SOI layer formed in this order and further including a local oxidation of silicon (LOCOS) having a birdbeak portion, by using an evaluation test element group (TEG), wherein said evaluation TEG comprises:
- a first electrode extending in a first direction and a second direction crossing said first direction;
- a second electrode spaced from the first electrode and extending in said first and second directions, wherein a first length of said second electrode in said first direction is substantially equal to a first length of said first electrode in said first direction and a second length of said second electrode in said second direction is different from a second length of said first electrode in said second direction;
- a third electrode spaced from said first and second electrodes and extending in said first and second directions, wherein a first length of said third electrode in said first direction is substantially equal to said first length of said first electrode and a second length of said third electrode in said second direction is substantially equal to a length of said birdbeak portion in said second direction;
- and
- a plurality of test pads electrically connected to said first, second, and third electrodes, respectively, wherein said second lengths of said first and second electrodes are larger than said length of said birdbeak portion to the extent that said length of said birdbeak portion can be disregarded, said method comprising:
- disposing said TEG on said SOI layer via an oxide film;
- and
- finding a capacitance of said birdbeak portion in a third direction perpendicular to said first and second directions by applying a voltage between said test pads and said substrate.
An evaluation TEG for evaluating a semiconductor device having a substrate;
- a dielectric layer;
- an SOI layer formed in this order and further including a local oxidation of silicon (LOCOS) having a birdbeak portion, comprising:
- a first electrode extending in a first direction and a second direction crossing the first direction, said first electrode having a first length along the first direction and a second length along the second direction larger than a length of the birdbeak portion along the second direction;
- a second electrode spaced from the first electrode and extending in the first and second directions, said second electrode having a third length along the first direction substantially equal to the first length, and a fourth length along the second direction different from the second length and larger than the length of the birdbeak portion along the second direction;
- a third electrode spaced from the first and second electrodes and extending in the first and second directions, said third electrode having a fifth length along the first direction substantially equal to the first length, and a sixth length along the second direction substantially equal to the length of the birdbeak portion along the second direction;
- and
- a plurality of test pads electrically connected to the first, second, and third electrodes, respectively.
Dependencies are inferred from the claim text.