Structure of delta-sigma fractional type divider
AssigneeElectronics and Telecommunications Research Institute
InventorsSeon-Ho Han, Jang-Hong Choi, Jae-Hong Jang, Hyun-Kyu Yu
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Abstract
The present invention relates to a structure of a delta-sigma fractional type divider. The divider structure adds an external input value and an output value of a delta-sigma modulator to modulate a value of a swallow counter. Therefore, the present invention can provide a delta-sigma fractional type divider the structure is simple and that can obtain an effect of a structure of a delta sigma mode while having a wide-band frequency mixing capability.
Claims15
A delta-sigma fractional type divider, comprising:
- a delta-sigma modulator for receiving a clock signal and a first digital value to perform a delta-sigma modulation, said first digital value being used to program a fractional ratio frequency of a frequency synthesizer;
- a swallow adder group for receiving an output value of said delta-sigma modulator and a second digital value to add an integer dividing ratio of a swallow counter and said output value of said delta-sigma modulator, said second digital value being used to program an integer ratio frequency of the frequency synthesizer;
- a program register group for storing an output value of said swallow adder group;
- and
- a pulse swallow counter group having a dual modulus prescaler, a program counter and said swallow counter, for dividing an input frequency depending on said value stored by said program register group.
A delta-sigma fractional type divider, comprising:
- a modulator configured to use a first digital value to program a fractional ratio frequency of a frequency synthesizer;
- an adder group configured to use an output value of said modulator and a second digital value, said second digital value being used to program an integer ratio frequency of the frequency synthesizer;
- a program register group configured to store an output value of said adder group;
- and
- a counter group configured to divide an input frequency depending on said value stored by said program register group.
A method for delta-sigma fractional type dividing comprising:
- receiving a clock signal and a first digital value to perform a delta-sigma modulation, said first digital value being used to program a fractional ratio frequency of a frequency synthesizer;
- adding an integer dividing ratio of a counter and an output value of said modulator to produce a second output value;
- receiving a second digital value to program an integer ratio frequency of the frequency synthesizer;
- storing the second output value using a program register group;
- and
- dividing an input frequency depending on said value stored by said program register group.
Dependencies are inferred from the claim text.