Semiconductor device and timing control circuit

A clock signal generating circuit comprising:

• a clock forming circuit including,
• a first delay circuit which receives a first clock having a first cycle and thereby outputs a second clock obtained by delaying the first clock;
• a second delay circuit which outputs a second signal obtaining by delaying a first signal in response to the second signal;
• and
• a control circuit which determines the state of the second signal at the time that a third clock having a second cycle has changed from a first level to a second level, in response to the third clock and the second signal, and outputs a control signal based on the result of determination to said first delay circuit;
• and
• wherein said second delay circuit is set to an initial state in response to a fourth clock having the second cycle and formed on one semiconductor substrate.

A semiconductor memory, comprising:

• a clock forming circuit including a first variable delay circuit which receives a first clock signal and outputs a second clock signal obtained by delaying said first clock signal;
• a second variable delay circuit which receives a first signal and outputs a second signal obtained by delaying said first signal;
• a first delay circuit which receives said second signal and outputs a third signal;
• a control circuit which compares said third signal and a fourth signal and controls said first variable delay circuit in accordance with the compared result;
• and
• a signal generator which outputs said first and fourth signals, wherein said second variable delay circuit is able to be reset so that the remaining signal in said second variable delay circuit is erased after said control circuit compares said third signal and said fourth signal.

A semiconductor memory, comprising:

• a clock forming circuit including,
• a first variable delay circuit which receives a first clock and outputs a second clock obtained by delaying said first clock;
• a second variable delay circuit which receives a first signal and outputs a second signal obtained by delaying said first signal;
• a first delay circuit which receives said second signal and outputs a third signal;
• a control circuit which compares said third signal and a fourth signal and controls said first variable delay circuits in accordance with the compared result;
• and
• a signal generator which outputs said first and fourth signals, wherein said first delay circuit is able to be reset so that the remaining signal in said first delay circuit is erased after said control circuit compares said third signal and said fourth signal.

A semiconductor memory, comprising:

• a clock forming circuit including, a first variable delay circuit which receives a first clock and outputs a second clock obtained by delaying said first clock;
• a first delay circuit which receives a first signal and outputs a second signal obtained by delaying said first signal, said first delay circuit having a second variable delay circuit and second delay circuit which are connected in series;
• a control circuit which compares said second signal and a third signal and controls said first variable delay circuits in accordance with the compared result;
• and
• a signal generator which outputs said first and third signals, wherein said second variable delay circuit is able to be reset thereby the remaining signal in said second variable delay circuit is erased after the comparing operation of said control circuit.