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US RE39,252 E1Granted
Instruction dependent clock scheme
AssigneeIntel Corporation
InventorVishram P. Dalvi
Life of this patent
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Abstract
A method and apparatus including a first circuit configured to receive multiple instructions including a first instruction having a first execution time, and to generate a first signal having a state dependent on the first execution time; a second circuit configured to receive the first signal and to generate a clock signal including a clock cycle having a period dependent on the state of the first signal; and a third circuit configured to receive the clock signal and execute a portion of the first instruction during the clock cycle, the first execution time corresponding to the portion of the first instruction.
Claims25
A method comprising the steps of:
- fetching a first instruction of a plurality of instructions, each of said instructions having execution times for at least one fetch step, at least one decode step, and at least one execution step;
- determining whether the execution time of the execution step of the first instruction is less than a first predetermined duration, said first predetermined duration set such that the execution time of any fetch and decode step is less than the first predetermined duration;
- if the execution time of the execution step is less than the first predetermined duration, configuring a clock cycle to correspond to the first predetermined duration;
- and
- if the execution time of the execution step is not less than the first predetermined duration, configuring the clock cycle to correspond to a second predetermined duration, said second predetermined duration set such that the execution time of any fetch, decode and execution step is less than the second predetermined duration.
2 more elements
A method comprising the steps of:
- fetching a first instruction, having at least one execution time for at least one step selected from the group consisting of a fetch step, a decode step, an execution step or a writeback step;
- decoding the first instruction, and using information derived from the decode to select from at least 2 available clock periods, the selected clock period providing enough time to concurrently execute a combination of steps selected from the group consisting of a fetch step, a decode step, an execution step or a writeback step;
- and
- concurrently executing a combination of steps selected from the group consisting of a fetch step, a decode step, an execution step or a writeback step.
1 more element
An apparatus comprising:
- means for fetching a first instruction of a plurality of instructions, each of said instructions having execution times for at least one fetch step, at least one decode step, and at least one execution step;
- means for determining whether the execution time of the execution step of the first instruction is less than a first predetermined duration, said first predetermined duration set such that the execution time of any fetch and decode step is less than the first predetermined duration, and if the execution time of the execution step is less than the first predetermined duration, a clock cycle is configured to correspond to the first predetermined duration;
- and if the execution time of the execution step is not less than the first predetermined duration, then the clock cycle is configured to correspond to a second predetermined duration, said second predetermined duration set such that the execution time of any fetch, decode and execution step is less than the second predetermined duration.
An apparatus comprising:
- means for fetching a first instruction, having at least one execution time for at least one step selected from the group consisting of a fetch step, a decode step, an execution step or a writeback step;
- means for decoding the first instruction and using information derived from the decode to select from at least 2 available clock periods, the selected clock period providing enough time to concurrently execute a combination of steps selected from the group consisting of a fetch step, a decode step, an execution step of a writeback step;
- and
- means for concurrently executing a combination of steps selected from the group consisting of a fetch step, a decode step, an execution step or a writeback step.
1 more element
An apparatus comprising:
- a fetching unit for fetching a first instruction of a plurality of instructions, each of said instructions having execution times for at least one fetch step, at least one decode step, and at least one execution step;
- a decode unit for determining whether the execution time of the execution step of the first instruction is less than a first predetermined duration, said first predetermined duration set such that the execution time of any fetch and decode step is less than the first predetermined duration, and if the execution time of the execution step is less than the first predetermined duration, a clock cycle is configured to correspond to the first predetermined duration;
- and if the execution time of the execution step is not less than the first predetermined duration, then the clock cycle is configured to correspond to a second predetermined duration, said second predetermined duration set such that the execution time of any fetch, decode and execution step is less than the second predetermined duration.
An apparatus comprising:
- a decode unit to determine whether an execution time of an execution step of a first instruction is less than a first predetermined duration, said first predetermined duration set such that the execution time of any fetch and decode step is less than the first predetermined duration, and if the execution time of the execution step is less than the first predetermined duration, a clock cycle is configured to correspond to the first predetermined duration;
- and if the execution time of the execution step is not less than the first predetermined duration, then the clock cycle is configured to correspond to a second predetermined duration, said second predetermined duration set such that the execution time of any fetch, decode and execution step is less than the second predetermined duration.
Dependencies are inferred from the claim text.