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US RE39,016 E1Granted
Memory module assembly using partially defective chips
AssigneeCeletron USA, Inc.
InventorCharles I. Peddle
Life of this patent
Estimating the term…
Abstract
Methods and devices for using less-than-perfect memory chips and packages in the manufacture of memory modules. In the preferred method the failed I/O lines in primary memory packages are disconnected and replaced by selected I/O lines from flawless or partially defective backup parts all mounted on the same module. The various processes comprise sorting of partially defective parts according to the results of wafer or packages test, judicious distribution of backup parts on a PC board module and routing of their I/O lines, optimized patching techniques and multi-level tests and repatching routines. The methods and processes are equally applicable to Chip On Board assemblies as well as package assemblies.
Claims109
A method for developing a fully functional transparent memory module comprising an assembly of selected independent primary and backup memory parts,
- the method comprising the steps of:
- testing a plurality of independent memory parts for failed I/O data line segments;
- sorting the parts according to the results of the testing;
- identifying failed and working I/O data line segments in the sorted parts;
- selecting at least one primary part having at least one I/O data line failure, and at least one different partially defective backup memory part from said sorted parts;
- and
- combining working I/O data line segments of different selected memory parts, including at least one working I/O data line segment of at least one partially defective backup memory part and working I/O data line segments of a primary part to form a fully functional transparent memory module.
4 more elements
A method for developing effective chip-on-board memory modules comprising an assembly of a selected combination of independent partially defective memory chips,
- comprising the steps of:
- assembling the selected chips as primary chips and backup chips onto a chip-on-board memory module assembly;
- testing the assembled module for failed I/O data lines in the chips;
- identifying operating I/O data line segments in the chips;
- and
- combining identified working I/O data line segments of a partially defective primary chip with a required number of working I/O data line segments of backup memory chips.
3 more elements
A method for patching selected partially defective independent primary memory parts with selected different partially defective independent backup memory parts to form a memory module functionally transparent to the user, comprising the steps of:
- testing the primary memory parts and the backup memory parts before mounting the parts on a board to;
- identify operating and failed I/O data line segments of the primary parts and of the backup memory parts;
- determining which operating I/O data lines from the backup memory parts to use for selectively patching failed I/O data lines segments of the primary memory parts;
- and
- substituting said determined operating I/O data lines from the backup parts for failed I/O data lines in one or more primary parts to form a completed memory module.
2 more elements
A method for patching primary parts with partially defective parts, comprising the steps of:
- perform a wafer test on memory die;
- identify the working and nonworking segments in the parts;
- package the primary and partially defective parts according to working segments;
- test the parts;
- give each part an identification code, the identification code containing a quadrant test pattern of the part;
- select parts for assembly on a module board;
- assemble the parts on the module board according to the nature and location of the parts' working segments;
- fill in the solder-dot locations of the primary parts, wherein the solder-dot locations of the back-up parts are left open;
- test the module on a full function circuit tester, wherein failed bits are noted, and the module is assigned a new identification code designating the failed bits;
- generate patching instruction charts for the module, wherein the development of the patching instruction charts includes an optimization pass designed to maximize use of smaller patch parts, leaving the larger parts available for patching later-discovered failures;
- disconnect solder-dot connections on the primary parts to isolate the failed line;
- fill the solder-dot connections to patch in the substitute lines, the solder-dot connections selected as identified in the patching instruction charts;
- and
- re-test the module, including high temperature stress testing of the module.
11 more elements
A method for generating patching instruction traveler charts using optimization, comprising the following steps:
- scanning bits of wider parts;
- identifying unused bits in the smaller parts, wherein the unused bits will be used for substitution;
- optimizing the selection of the parts to use in patching;
- generating patching instructions;
- and
- implementing the generated patching instructions into a traveler chart.
3 more elements
A module made up of primary parts and partially defective backup parts, comprising:
- at least one primary part, the primary part having at least one line failure;
- a plurality of partially defective parts;
- a module PC board containing a pattern of solder-dot connections, the solder-dot connections allowing any failing primary part I/O lines to be replaced by I/O substitute lines from the backup parts.
A SIMM module made up of primary parts and partially defective parts, comprising:
- at least two primary parts, at least one of the primary parts having at least one line failure;
- a plurality of partially defective parts;
- a module PC board containing a pattern of solder-dot connections, the solder-dot connections allowing the failing primary part lines to be replaced by I/O substitute lines from the partially defective parts;
- wherein the failing line is disconnected from the primary part by removing the solder of its solder dot connection and the substitute line is connected by filling the applicable solder-dot, the substitute line having the equivalent function as the failing line so that the module is transparent to the user.
1 more element
A memory module made up of primary parts and partially defective backup parts, comprising:
- four primary parts, each of the primary parts having at least one line failure;
- eight partially defective backup parts;
- a module PC board containing a pattern of solder-dot connections, the solder-dot connections allowing the failing primary part lines to be replaced by I/O substitute lines from the backup parts;
- wherein the failing line is disconnected from the primary part by removing the solder of its solder dot connection and the substitute line is connected by filling the applicable solder-dot, the replacement line having the equivalent function as the failing line so that the module is transparent to the user.
1 more element
A chip-on-board module made up of primary parts and partially defective backup parts, comprising:
- at least one primary part, the primary part having at least one line failure;
- a plurality of partially defective parts;
- a module PC board containing a pattern of solder-dot connections, the solder-dot connections allowing any failing primary part I/O lines to be replaced by I/O substitute lines from the backup parts;
- wherein the failing line is disconnected from the primary part by removing the solder of its solder dot connection and the substitute line is connected by filling the applicable solder-dot, the replacement line having the equivalent function as the failing line so that the chip-on-board module is transparent to the user.
1 more element
A method for selecting and assembling primary parts and backup parts on a chip-on-board module assembly comprising patterns of solder dot locations for the primary and backup parts, the process comprising the steps of:
- performing a wafer test on a memory die;
- selecting, as primary parts, partially defective dies that have a reasonable probability of being patched successfully;
- selecting, as backup parts, other partially defective dies that test to be suitable for patching;
- assembling the selected primary and backup parts on the PC module;
- applying a plastic over coating to the assembled parts;
- and
- testing the module using a chip test applied at the module pins;
- and
- patching failed segments of the primary parts with working segments of the backup parts.
6 more elements
A method for selecting and assembling primary parts and backup parts on a chip-on-board module assembly comprising patterns of solder dot locations for the primary and backup parts,
- the process comprising the steps of:
- performing a wafer test on a memory die;
- selecting, as primary parts, dies that have a reasonable probability of being patched successfully;
- selecting, as backup parts, other dies for assembly on a PC module;
- assembling the selected primary and backup parts on the PC module;
- applying a plastic over coating to the assembled parts;
- and
- test the module using a chip test applied at the module pins;
- assigning a bar code to the module to identify failed bits;
- fill in the solder-dot locations of the primary parts, the solder-dot locations of the back-up parts are left open;
- test the module on a full function circuit tester, wherein failed bits are noted, and the module is assigned a bar-code identifying the failed bits;
- generate patching instruction charts for the module, wherein the development of the patching instruction charts includes an optimization pass designed to maximize use of smaller patch parts, leaving the larger parts available for patching later-discovered failures;
- disconnect solder-dot connections on the primary parts to isolate any failed line;
- fill the solder-dot connections to patch in substitute lines, the solder-dot connections selected as identified in the patching instruction charts;
- re-test the module, including high temperature stress testing of the module.
12 more elements
A memory module made up of primary parts and partially defective backup parts, comprising:
- at least four primary parts, the primary parts having at least one line failure, and the primary parts are laid out horizontally with a card edge;
- at least four partially defective parts;
- a module PC board containing a pattern of solder-dot connections, the solder-dot connections allowing any failing primary part I/O lines to be replaced by I/O substitute lines from the backup parts;
- wherein the failing line is disconnected from the primary part by removing the solder of its solder dot connection and the substitute line is connected by filling the applicable solder-dot, the replacement line having the equivalent function as the failing line so that the module is transparent to the user.
1 more element
A memory module comprising:
- primary part memory means for storing data;
- independent backup part memory means for storing data;
- connection means for selectively substituting an operational I/O data line of said backup memory means for a failed I/O data line of said primary memory means;
- said memory module has a target memory capability X,
- said primary part memory means has a memory capacity X minus the capacity of any defective I/O data lines therein;
- and
- said independent backup part memory means has available memory capacity at least equal to the capacity of said defective I/O data lines.
4 more elements
A method for constructing a fully functional memory module which utilizes partially defective independent memory circuit parts comprising:
- (a) testing and classifying memory parts in a set of defined classifications;
- (b) selecting a primary memory part having a selected classification;
- (c) selecting a backup memory part having a selected different classification;
- (d) constructing a memory module wherein any defective data lines of the selected primary memory part are replaced by operational data lines of the backup circuit structure;
- and
- (e) testing constructing step (d) comprises:
- providing a selected pattern of solder dot connections.
4 more elements
A method for constructing a fully functional memory module which utilizes partially defective independent memory circuit parts comprising:
- (a) testing and classifying memory parts in a set of defined classifications
- (b) selecting a primary memory part having a selected classification;
- (c) selecting a backup memory part having a selected different classification;
- (d) constructing a memory module wherein:
- any defective data lines of the selected primary memory part are replaced by operational data lines of the backup circuit structure;
- (e) testing said so constructed module as to its operational status to approve use of said module or to identify any operating problem in said module;
- (f) reconstructing said module to remove any identified operating problem;
- (g) testing said module as to its operational status to approve use as reconstructed or to identify any operating problems;
- and
- (j) (h) repeating steps (h) and (i) (f) and (g) as required until the module is approved for service.
7 more elements
A method of manufacturing a fully functional transparent memory module including an assembly of selected independent primary and independent backup memory parts, the method comprising the steps of:
- testing a plurality of independent memory parts to identify failed I/O data line segments and working I/O data line segments,
- sorting said tested memory parts into a plurality of categories by patterns of failed and working I/O data line segments,
- selecting at least one primary part having at least one failed I/O segment, and at least one partially defective backup part from said sorted parts, and
- combining working I/O data line segments of different selected primary parts and of partially defective backup parts to form a fully functional transparent memory module.
1 more element
A fully operational transparent memory module including primary parts and partially defective backup parts wherein said primary parts and said backup parts have been functionally tested and classified into a plurality of groups according to working I/O segments of said primary part and said backup parts, comprising:
- at least one primary part, said primary part having at least one failed output segment,
- at least one partially defective backup part, said backup part having a different group classification than said primary part to facilitate replacement of failed output segments of said primary part,
- a printed circuit module board having a pattern of conductive lines for forming electrical connections to the I/O output segments of said primary part, and
- connector for selectively interrupting output segments of said primary part and for replacement thereof with a working line segment of said backup part.
1 more element
A method for patching primary memory parts of a memory module with segments of partially defective backup memory parts to produce a fully operational transparent memory module, said method comprising the steps of:
- performing a wafer test on a plurality of independent memory die,
- identifying the respective working and non-working segments in each of said memory die,
- packaging said plurality of memory die into primary and backup memory parts according to working and non-working segments,
- selecting packaged parts for assembly on a printed circuit type board,
- assembling the selected parts on said printed circuit board in accordance with test data identifying working segments of said parts,
- selectively connecting output segments of the primary memory parts to said printed circuit board connectors,
- subjecting the assembled primary parts to a full function circuit test to determine any failed output bits,
- generating patching instructions to optimize repair of any failed output bits of said primary parts,
- disconnecting any failed output bits of said primary parts in accordance with said test results, and
- substituting working segments of said backup parts for failed bits of said primary parts in accordance with said patching instructions.
7 more elements
A SIMM memory module made up of primary parts and partially defective backup parts, comprising:
- at least two primary parts with at least one of the primary parts having at least one line failure,
- a plurality of partially defective independent backup parts,
- a printed circuit module board having conductive strips on at least one surface of said board, and
- connector means on said board for selectively disconnecting failed primary part lines to facilitate replacement thereof by substitute lines of said partially defective backup parts having an equivalent function as the failed line whereby the repaired memory module is fully functional and transparent to a user.
1 more element
A chip-on-board memory module made up of a plurality of primary die parts and a plurality of partially defective backup die parts, comprising:
- a printed circuit board having a plurality of conductors arranged on at least one surface for supporting said primary die parts and said backup die parts,
- at least one primary die part mounted on said printed circuit board and connected to selected ones of said conductors and said primary die part having at least one failed line,
- a plurality of partially defective backup die parts mounted on said printed circuit board in accordance with predetermined working and non-working line segments data,
- means for identifying the respective working and non-working lines of said primary and backup die parts, and
- connector means for selectively optimizing replacement of a non-working line of said primary part with a working line of said backup part having the equivalent function as said failed line so that the repaired memory module is fully functional and transparent to a user.
2 more elements
A semiconductor memory module fabricated to facilitate repair of defective components, the memory module comprising:
- a printed circuit-type board having a plurality of conductive pathways on at least one surface thereof and individual pathways being connected to I/O lines of said board,
- at least one primary memory die part mounted on said printed circuit board having individual leads thereof connected to individual ones of said conductive pathways,
- a plurality of independent partially defective backup memory die parts being mounted on said printed circuit board in positions determined in accordance with pre-assembly die test data to optimize backup capabilities of said backup memory die parts, and
- bit patching means for selectively rerouting ones of said conductive pathways to selectively replace a non-working I/O line of said primary memory die part with a working I/O line of one of said backup memory die parts having an equivalent function as said failed I/O line to form a fully functional memory module.
1 more element
A semiconductor memory module fabricated to facilitate repair of defective components, the memory module comprising:
- a printed circuit-type board having a plurality of conductive pathways on at least one surface thereof and the individual pathways being connected to I/O lines of said board,
- at least one primary memory die part mounted on said printed circuit board with predetermined leads electrically connected to pre-selected ones of said conductive pathways,
- a plurality of independent partially defective backup memory die parts positioned on said printed circuit board in accordance with pre-assembly die test data to optimize backup capabilities of said mounted backup die parts, and
- bit steering means for selectively combining working I/O lines of ones of said backup memory die parts and for electrically connecting said selected working I/O lines to replace non-working I/O lines of said primary die part to form thereby a fully functional memory module.
1 more element
Dependencies are inferred from the claim text.