US RE38,499 E1 · Two-stage amplifier for active pixel sensor cell array for reducing fixed pattern noise in the array output

An active pixel sensor cell array including at least a first cell and a second cell connected along a column, where the first cell is an active pixel sensor cell including a first photodiode and a reset circuit configured to reset the first photodiode in response to a reset signal, and the second cell is an active pixel sensor cell including a second photodiode and a second reset circuit configured to reset the second photodiode in response to a second reset signal, said array comprising:

a primary amplifier stage within the first cell, coupled to the first photodiode and configured to output a first amplified signal indicative of a sampled output voltage of said first photodiode;
a second primary amplifier stage within the second cell, coupled to the second photodiode and configured to output a second amplified signal indicative of a sampled output voltage of said second photodiode, wherein each of the primary amplifier stage and the second primary amplifier stage is a differential amplifier;
and
load circuitry, physically separate from the first cell and the second cell but coupled to both the primary amplifier stage and the second primary amplifier stage, including a secondary output amplifier stage configured to output a further amplified signal in response to any selected one of the first amplified signal and the second amplified signal, wherein the primary amplifier stage and the load circuitry together comprise an op amp, and the op amp has an output terminal at which the further amplified signal is output, wherein the primary amplifier stage has a first input coupled to the first photodiode and a second input to which the output terminal of the op amp is coupled, and wherein the array is operable in a mode in which the further amplified signal is output at the output terminal of the op amp and is fed back to the second input of the primary amplifier stage.

1 more element

An active pixel sensor cell array including at least a first cell and a second cell connected along a column, where the first cell is an active pixel sensor cell including a first photodiode and a reset circuit configured to reset the first photodiode in response to a reset signal, and the second cell is an active pixel sensor cell including a second photodiode and a second reset circuit configured to reset the second photodiode in response to a second reset signal, said array comprising:

a primary amplifier stage within the first cell, coupled to the first photodiode and configured to output a first amplified signal indicative of a sampled output voltage of said first photodiode;
a second primary amplifier stage within the second cell, coupled to the second photodiode and configured to output a second amplified signal indicative of a sampled output voltage of said second photodiode, wherein each of the primary amplifier stage and the second primary amplifier stage is a differential amplifier;
and
load circuitry, physically separate from the first cell and the second cell but coupled to both the primary amplifier stage and the second primary amplifier stage, including a secondary output amplifier stage configured to output a further amplified signal in response to any selected one of the first amplified signal and the second amplified signal, wherein each of the primary amplifier stage and the second primary amplifier stage includes NMOS transistors but no PMOS transistor, wherein the column includes a first column line, a second column line, a third column line, and a fourth column line, and wherein the load circuitry includes:
a first PMOS transistor having a source for coupling to a supply voltage, a drain coupled to a first end of the first column line, and a gate;
a second PMOS transistor having a source for coupling to the supply voltage, a drain coupled to a first end of the second column line, and a gate coupled to the gate of the first PMOS transistor and to the drain of the second PMOS transistor;
a third PMOS transistor having a gate coupled to a second end of the first column line, a source for coupling to the supply voltage, and a drain at which the further amplifier signal is output;
a first NMOS transistor having a drain coupled to the drain of the third PMOS transistor, a source for coupling to ground potential, and a gate;
and
bias circuitry coupled to the gate of the first NMOS transistor and configured to output a bias voltage to said gate of the first NMOS transistor.

7 more elements

An active pixel sensor cell array including at least a first cell and a second cell connected along a column, where the first cell is an active pixel sensor cell including a first photodiode and a reset circuit configured to reset the first photodiode in response to a reset signal, and the second cell is an active pixel sensor cell including a second photodiode and a second reset circuit configured to reset the second photodiode in response to a second reset signal, said array comprising:

a primary amplifier stage within the first cell, coupled to the first photodiode and configured to output a first amplified signal indicative of a sampled output voltage of said first photodiode;
a second primary amplifier stage within the second cell, coupled to the second photodiode and configured to output a second amplified signal indicative of a sampled output voltage of said second photodiode, wherein each of the primary amplifier stage and the second primary amplifier stage is a differential amplifier;
and
load circuitry, physically separate from the first cell and the second cell but coupled to both the primary amplifier stage and the second primary amplifier stage, including a secondary output amplifier stage configured to output a further amplified signal in response to any selected one of the first amplified signal and the second amplified signal, wherein the column includes at least a first column line, and the load circuitry includes:
a PMOS transistor having a gate coupled to an end of the first column line, a source for coupling to a supply voltage, and a drain at which the further amplified signal is output;
a first NMOS transistor having a drain coupled to the drain of the PMOS transistor, a source for coupling to ground potential, and a gate;
and
a bias circuit coupled to the gate of the first NMOS transistor and configured to output a bias voltage to the gate of the first NMOS transistor in response to a bias control signal, wherein the bias voltage undergoes a first transition which rapidly turns off the first NMOS transistor in response to transition of the bias control signal from a first level to a second level, and the bias voltage undergoes a second transition causing the first NMOS transistor to conduct a desired bias current in response to transition of the bias control signal from the second level to the first level.

5 more elements

An active pixel sensor cell array including at least a first cell and a second cell connected along a column including at least a first column line, where the first cell is an active pixel sensor cell including a first photodiode and a reset circuit configured to reset the first photodiode in response to a reset signal, and the second cell is an active pixel sensor cell including a second photodiode and a second reset circuit configured to reset the second photodiode in response to a second reset signal, said array comprising:

a primary amplifier stage within the first cell, coupled to the first photodiode and configured to output a first amplified signal indicative of a sampled output voltage of said first photodiode;
a second primary amplifier stage within the second cell, coupled to the second photodiode and configured to output a second amplified signal indicative of a sampled output voltage of said second photodiode;
and
load circuitry, physically separate from the first cell and the second cell but coupled to both the primary amplifier stage and the second primary amplifier stage, including a secondary output amplifier stage configured to output a further amplified signal in response to any selected one of the first amplified signal and the second amplified signal, wherein the load circuitry includes:
a PMOS transistor having a gate coupled to an end of the first column line, a source for coupling to a supply voltage, and a drain at which the further amplified signal is output;
a first NMOS transistor having a drain coupled to the drain of the PMOS transistor, a source for coupling to ground potential, and a gate;
and
a bias circuit coupled to the gate of the first NMOS transistor and configured to output a bias voltage to the gate of the first NMOS transistor in response to a bias control signal, wherein the bias voltage undergoes a first transition which rapidly turns off the first NMOS transistor in response to transition of the bias control signal from a first level to a second level, and the bias voltage undergoes a second transition causing the first NMOS transistor to conduct a desired bias current in response to transition of the bias control signal from the second level to the first level.

5 more elements

An active pixel sensor cell circuit, including:

an active pixel sensor cell including a photodiode, a reset circuit coupled to the photodiode and configured to reset the first photodiode in response to a reset signal, and a differential amplifier coupled to the photodiode and configured to output an amplified signal indicative of a sampled output voltage of said photodiode in response to a control signal;
load circuitry physically separate from the active pixel sensor cell, wherein the load circuitry is coupled to the differential amplifier for receiving the amplified signal amplifier stage, and the load circuitry includes a secondary output amplifier stage configured to output a further amplified signal in response to the amplified signal;
and
a first column line extending through the cell, a second column line extending through the cell, a third column line extending through the cell, and a fourth column line extending through the cell, wherein the reset circuit is coupled to the first column line,
wherein the differential amplifier has a first input coupled to the photodiode, a second input coupled to the third column line, and a tail current circuit coupled to the fourth column line and configured to sink a first tail current to said fourth column line in response to a row select signal, and wherein the load circuitry includes:
a first PMOS transistor having a source for coupling to a supply voltage, a drain coupled to a first end of the first column line, and a gate;
a second PMOS transistor having a source for coupling to the supply voltage, a drain coupled to a first end of the second column line, and a gate coupled to the gate of the first PMOS transistor and to the drain of the second PMOS transistor;
a third PMOS transistor having a gate coupled to a second end of the first column line, a source for coupling to the supply voltage, and a drain at which the further amplified signal is output;
a first NMOS transistor having a drain coupled to the drain of the third PMOS transistor, a source for coupling to ground potential, and a gate;
and
bias circuitry coupled to the gate of the first NMOS transistor and configured to output a bias voltage to said gate of the first NMOS transistor.

8 more elements

Two-stage amplifier for active pixel sensor cell array for reducing fixed pattern noise in the array output

Life of this patent

Two-stage amplifier for active pixel sensor cell array for reducing fixed pattern noise in the array output

Life of this patent

Abstract

Claims25