Delay stage circuitry for a ring oscillator

A ring oscillator comprising:

• a plurality of ring coupled delay stages, each delay stage comprising:
• (A) a differential amplifier for generating a first output signal at a first node and a second output signal at a second node, wherein the differential amplifier further comprises:
• (i) a first transistor coupled between the first node and a first potential;
• (ii) a second transistor coupled between the second node and the first potential, wherein the first and second transistors are biased by an output level biasing voltage;
• (iii) a third transistor coupled between the first node and a third node, wherein the third transistor receives a first input signal from a preceding delay stage;
• (iv) a fourth transistor coupled between the second node and the third node, wherein the fourth transistor receives a second input signal from the preceding delay stage;
• (B) a current source coupled between the third node and a second potential, the current source varying a bias current through the current source in accordance with a delay bias voltage;
• and
• (C) a voltage clamping circuit coupled to the first and second nodes to limit a relative peak-to-peak voltage swing of the first and second output signals without independently clamping each of the first and second nodes.

A ring oscillator comprising:

• a plurality of ring coupled delay stages, each delay stage comprising:
• a differential amplifier providing a differential output signal;
• a self-biased voltage clamping circuit coupled to limit a peak-to-peak voltage swing of the differential output signal;
• and
• a current source coupled to the differential amplifier, the current source varying a bias current through the current source in accordance with a delay bias voltage.

A ring oscillator comprising:

• a plurality of ring coupled delay stages, each delay stage comprising:
• a differential amplifier providing a differential output signal comprising a first output signal at a first node and a second output signal at a second node;
• a voltage clamping circuit coupled to the first and second nodes to limit a peak-to-peak voltage swing of the differential output signal without independently clamping each of the first and second nodes;
• and
• a current source coupled to the differential amplifier, the current source varying a bias current through the current source in accordance with a delay bias voltage.

A synchronous memory device comprising:

• an array of memory cells to store data;
• a clock synchronization loop to generate a plurality of clock signals, each clock signal having a timing relationship with respect to a reference clock signal;
• first interpolator circuitry to generate a first internal clock signal from a first and a second clock signal of the plurality of clock signals, wherein a phase of the first internal clock signal is interpolated from respective phases of the first and second clock signals according to phase information indicative of whether the first internal clock signal leads or lags a first external clock signal;
• and
• interface circuitry to synchronize a transmission of data with the first internal clock signal.

An integrated circuit device comprising:

• interface circuitry to receive first and second external clock signals;
• and
• clock synchronization circuitry to synchronize a transmission of data with the first external clock signal and to synchronize a reception of data with the second external clock signal, the clock synchronization circuitry including:
• a reference loop to receive a reference clock signal and generate a plurality of clock signals, each clock signal of the plurality of clock signals having a predetermined timing relationship with the reference clock signal;
• a first subloop circuit, coupled to the reference loop, to synchronize the transmission of data with the first external clock signal using the plurality of clock signals;
• and
• a second subloop circuit, coupled to the reference loop, to synchronize the reception of data with the second external clock signal using the plurality of clock signals.

A clock synchronization circuit comprising:

• a plurality of delay stages coupled in series to output a plurality of clock signals, each delay stage having a delay time with respect to a reference clock signal;
• interpolator circuitry to generate a first clock signal using a pair of clock signals of the plurality of clock signals, wherein a phase of the first clock signal is interpolated between respective phases of each clock signal of the pair of clock signals in accordance with information indicative of whether a phase of the first clock signal leads or lags a phase of an input clock signal;
• and
• a detector circuit to compare the phase of the first clock signal with the phase of the input clock signal, to generate the information indicative of whether the phase of the first clock signal leads or lags the phase of the input clock signal.

A synchronous memory device comprising:

• an array of memory cells to store data;
• clock synchronization circuitry including:
• a plurality of delay stages coupled in series;
• a first multiplexer circuit, coupled to the plurality of delay stages, to perform selection of a delay time for a first internal clock signal, the selection being controlled by a first plurality of control signals;
• a first shift register circuit to generate the first plurality of control signals in accordance with information indicative of whether a phase of an external clock signal leads or lags a phase of an internal transmit clock signal;
• and
• a detector circuit to compare the phase of the external clock signal with the phase of the internal transmit clock signal and generate the information;
• and
• interface circuitry to output data from the memory device, the data being output in synchronism with the internal transmit clock signal, the internal transmit clock signal being generated using the first internal clock signal.

A synchronous memory device comprising:

• an array of memory cells to store data;
• a plurality of delay elements coupled in series, each delay element generating a respective output signal having a different phase;
• a detector circuit to compare a phase of an external clock signal with a phase of an internal transmit clock signal, the detector circuit to generate information indicative of whether the phase of the external clock signal leads or lags the phase of the internal transmit clock signal;
• a multiplexer circuit, coupled to the plurality of delay elements, to select a first output signal generated by the plurality of delay elements in response to the information;
• and
• an interface circuit to output data from the memory device, the data being output in synchronism with the internal transmit clock signal, the internal transmit clock signal being generated using at least the first output signal selected by the multiplexer circuit.

A method for clock synchronization, comprising:

• generating a plurality of clock signals from a reference clock signal, wherein each clock signal of the plurality of clock signals is delayed from the reference clock signal by a corresponding delay time such that a plurality of different delays with respect to the reference clock signal are represented in the plurality of clock signals;
• detecting phase of an input signal, wherein the phase of the input signal represents a target phase;
• and
• generating a first clock signal based on a pair of clock signals of the plurality of clock signals, wherein generating the first clock signal includes interpolation between the pair of clock signals using information indicative of whether the phase of the first clock signal leads or lags the target phase.

An integrated circuit comprising:

• a plurality of delay stages coupled in series to output a plurality of clock signals, each delay stage of the plurality of delay stages having a delay time with respect to a reference clock signal;
• a phase detector to determine the phase of an input signal by sampling the input signal, wherein the phase of the input signal is based on at least one transition in the input signal, the phase detector to generate information indicative of whether a phase of a first clock signal leads or lags the phase of the input signal;
• and
• interpolator circuitry coupled to the plurality of delay stages and the phase detector, the interpolator circuitry to generate the first clock signal using a pair of clock signals of the plurality of clock signals, wherein the phase of the first clock signal is interpolated between respective phases of the pair of clock signals in accordance with the information indicative of whether the phase of the first clock signal leads or lags the phase of the input signal.