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US RE38,379 E1Granted
Semiconductor memory with alternately multiplexed row and column addressing
AssigneeHitachi, Ltd.
InventorsKouji Hara, Ryoichi Kurihara
Life of this patent
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Abstract
The semiconductor memory receives an external clock signal and has the memory cell array access operation controlled based on the clock signal. In the application of this semiconductor memory to a dynamic RAM, for example, a row address and column address are introduced in synchronism with the clock signal. The read, write and refresh operations are controlled based on the clock signal.
Claims33
A semiconductor memory chip, comprising:
- a memory cell array;
- means of receiving an address signal having a row address signal and a column address signal in such a manner that the row address signal is received first and then the column address signal is subsequently received;
- means of communication with the outside for inputting and outputting data to and from said memory cell array;
- means for receiving a clock signal having a series of clock pulses;
- means for receiving a chip select signal from the outside which represents that the semiconductor memory is selected;
- means responsive to the clock signal and the chip select signal for generating a row address set signal and a column address set signal, wherein the row address set signal is generated under a circumstance where the semiconductor memory receives a firstly occurred clock pulse of the series of the clock pulses of the clock signal while the chip select signal is being provided to the semiconductor memory, and wherein the column address set signal is generated under a circumstance where the semiconductor memory receives a subsequent clock pulse while the chip select signal is being provided to the semiconductor memory;
- means responsive to the row address set signal for setting the address signal from the means of receiving as the row address signal and for providing the memory cell array with the set row address signal;
- and
- means responsive to the column address set signal for setting the address signal from the means of receiving as the column address signal and for providing the memory cell array with the set column address signal.
6 more elements
A semiconductor RAM chip, comprising:
- an address input terminal for receiving an address signal having row and column addresses time multiplexed;
- a chip select input terminal for receiving a chip select signal to indicate the selection of the semiconductor RAM;
- a clock input terminal for receiving a clock having a single periodic succession of clock pulses;
- a memory cell array;
- a data output terminal connected to said memory cell array to output data from said memory cell;
- a data input terminal connected to said memory cell array for receiving data for said memory cell;
- a row address decoder having a row address input and an output connected to said memory cell array;
- a column address decoder having a column address input and an output connected to said memory cell array;
- and
- means for receiving the multiplexed address signal from said address input terminal and the clock from said clock input terminal, and for outputting the row address to the input of the row address decoder separate from the column address and outputting the column address to the input of the column address decoder separate from the row address in response to only the clock when the chip select signal at said chip select input terminal indicates the selection of the semiconductor RAM.
7 more elements
A semiconductor memory chip, comprising:
- an address input terminal for receiving an address signal having row and column addresses time multiplexed;
- an input terminal for receiving a control signal that is selectively active;
- a clock input terminal for receiving a clock having a single periodic succession of clock pulses;
- a memory cell array;
- a data output terminal connected to said memory cell array to output data from said memory cell array;
- a row address decoder having a row address input and an output connected to said memory cell array;
- a column address decoder having a column address input and an output connected to said memory cell array;
- and
- demultiplexing means for receiving the multiplexed address signal from said address input terminal and the clock from said clock input terminal, and for outputting the row address to the input of the row address decoder separate from the column address and outputting the column address to the input of the column address decoder separate from the row address in response to only the timing of the clock when the control signal at said input terminal is active.
6 more elements
A semiconductor dynamic memory chip, comprising:
- a dynamic type random access memory cell array:
- an address input terminal to be supplied with address signals having time multiplexed row address signals and column address signals;
- a row address latch having an input which is supplied with said row address signals from said address input terminal;
- a column address latch having an input which is supplied with said column address signals from said address input terminal;
- a first latch circuit having an input which is supplied with an external chip select signal and a latch timing control terminal which is supplied with an external clock signal having a continuous succession of clock pulses of constant period;
- a second latch circuit having an input which is supplied with a write enable signal and a latch timing control terminal which is supplied with said external clock signal;
- a data input latch circuit having a data input which is supplied with an external data, a latch timing control terminal which is supplied with said external clock signal and a data output terminal which is coupled with said dynamic type random access memory cell array;
- a data output latch circuit having a data input which is coupled with said dynamic type random access memory cell array, an output timing control terminal which is supplied with said external clock signal and a data output terminal;
- a row address decoder having an input which is coupled with an output of said row address latch and an output which is coupled with said dynamic type random access memory cell array;
- and
- a column address decoder having an input which is coupled with an output of said column address latch and an output which is coupled with said dynamic type random access memory cell array,
- wherein said row address latch latches said row address signals in response to said external chip select signal latched by said first latch circuit and to a first level change of said external clock signal, and
- wherein said column address latch latches said column address signals in response to said external chip select signal latched by said first latch circuit and to a second level change which appears after said first level change of said external clock signal.
10 more elements
Dependencies are inferred from the claim text.