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US RE38,319 E1Granted
Dual-node capacitor coupled MOSFET for improving ESD performance
AssigneeWinbond Electronics Corp.
InventorsShin-Tron Lin, Shyh-Chyi Wong
Life of this patent
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AssigneeWinbond Electronics Corp.
InventorsShin-Tron Lin, Shyh-Chyi Wong
Estimating the term…
A dual-node capacitor coupling technique is used to lower the trigger voltage and to improve the uniform turn-on of a multi-finger MOSFET transistor. Preferably, each MOSFET is an NMOS device. Specifically, each NMOS device includes a capacitor that is connected between the gate of the NMOS device and the pad terminal. A first resistor is connected between the gate and the p-well, while a second resistor is connected between the p-well and the grounded source. For a positive ESD pulse to VSS, the p-well is pulled up to approximately 0.7 V during the initial ESD event, such that the source junction is forward biased and that the trigger voltage of the NMOS device is lowered. At the same time the gate voltage is coupled within the range of approximately 1 to 2 V to promote the uniform turn on of the gate fingers of the NMOS devices during the initial ESD event.
An ESD protection circuit for lowering the trigger voltage and improving the turn-on consistency of a MOSFET device, comprising:
An ESD protection circuit for lowering the trigger voltage and improving the turn-on consistency of a MOSFET device, comprising:
An ESD protection structure, comprising:
An ESD protection circuit for an integrated circuit, comprising:
An ESD protection circuit, comprising:
Dependencies are inferred from the claim text.