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US RE38,296 E1Granted
Semiconductor memory device with recessed array region
AssigneeHitachi, Ltd.
InventorsNoboru Moriuchi, Yoshiki Yamaguchi, Toshihiko Tanaka, Norio Hasegawa, Yoshifumi Kawamoto, Shin-ichiro Kimura, Toru Kaga, Tokuo Kure
Life of this patent
Estimating the term…
Abstract
A semiconductor memory wherein a memory cell region having a plurality of memory cells and a relatively high altitude above the surface of semiconductor substrate is formed at a recessed part of the semiconductor substrate having the recessed part and a projected part, and wherein a peripheral circuit region having a comparatively low altitude from the surface of the semiconductor substrate is formed at the projected part of the semiconductor substrate.
Claims44
A semiconductor memory comprising:
- (a) a semiconductor substrate having a major surface which includes a recessed part and a projected part;
- (b) a memory array having a plurality of memory cells, each of which includes a first MISFET of N-type conductivity and a capacitor connected in series, said first MISFET comprising a first gate electrode, first source and drain regions, of n-type conductivity, and said capacitor comprising first and second electrodes and a dielectric film therebetween, wherein said first and second electrodes and said dielectric film are formed over said major surface of said semiconductor substrate and over said first gate electrode of said first MISFET;
- and
- (c) a peripheral circuit including a plurality of second MISFETs of N-type conductivity, each having a second gate electrode and second source and drain regions of N-type conductivityand third MISFETs of P-type conductivity each having a third gate electrode and third source and drain regions of P-type conductivity ,
- wherein said first MISFETs and said capacitors of memory cells are formed on said recessed part of said major surface and said second MISFETs of said peripheral circuit is are formed on said projected part of said major surface, and
- wherein an altitude difference between said recessed part and said projected part of said major surface is set to a predetermined value based upon a depth of focus of a predetermined exposure apparatus used for forming said first and second MISFETs so that predetermined areas of both said first and second MISFETs will be with within said depth of focus of the predetermined exposure apparatus to permit simultaneous processing of said predetermined areas of said first and second MISFETs during formation of said first and second MISFETs.
3 more elements
A semiconductor memory comprising:
- (a) a semiconductor substrate having a major surface which includes a recessed part and a projected part;
- (b) a memory array having a plurality of data lines extending in column direction, a plurality of word lines extending in a row direction and a plurality of memory cells including first MISFETs of N-type conductivity;
- and
- (c) a peripheral circuit having a plurality of second MISFETs of N-type conductivity, third MISFETs of P-type conductivity, and first wiring lines formed by the same layer as said data lines and over said second and third MISFETs, wherein said first wiring lines and the data lines are formed at the same wiring layer level,
- wherein said first MISFETs are formed on said recessed part of said major surface and said second second and third MISFETs are formed on said projected part of said major surface, and
- wherein an altitude difference between said recessed part and said projected part of said major surface is set to a predetermined value based upon a depth of focus of a predetermined exposure apparatus used for forming said first and second first, second and third MISFETs so that predetermined areas of both said first and second first, second and third MISFETs will be within said depth of focus of the predetermined exposure apparatus to permit simultaneous processing of said predetermined areas of said first and second first, second and third MISFETs during formation of said first and second first, second and third MISFETs.
3 more elements
A semiconductor memory comprising:
- (a) a semiconductor substrate having a major surface which includes a recessed part and a projected part;
- (b) a memory array having a plurality of memory cells each of which includes a first MISFET and a capacitor connected in series, said first MISFET comprising a first gate electrode, a first source region and a first drain region, and said capacitor comprising first and second electrodes and a dielectric film therebetween, wherein said first and second electrodes and said dielectric film are formed over said major surface of said semiconductor substrate and over said first gate electrode of said first MISFET;
- and
- (c) a peripheral circuit including a plurality of second MISFETs, each having a second gate electrode and a second source region and a second drain region,
- wherein said first MISFETs and said capacitors of memory cell cells are formed on said recessed part of said major surface and said second MISFETs of said peripheral circuit are formed on said projected part of said major surface, and further wherein an altitude difference between said recessed part and said projected part of said major surface is set to a predetermined value based upon a depth of focus of a predetermined exposure apparatus used for forming said first and second MISFET MISFETs so that predetermined areas of both said first and second MISFETs will be within said depth of focus of the predetermined exposure apparatus to permit simultaneous processing of said predetermined areas of said first and second MISFET MISFETs during formation of said first and second MISFETs.
2 more elements
A semiconductor memory comprising:
- (a) a semiconductor substrate having a major surface which includes a recessed part and a projected part;
- (b) a memory array having a plurality of data lines extending in column direction, a plurality of word lines extending in row direction and a plurality of memory cells including first MISFETs;
- and
- (c) a peripheral circuit having a plurality of second MISFETs and first wiring lines formed by the same layer as said data lines and over said second MISFETs, wherein the first wiring lines and the data lines are formed at the same wiring layer level,
- wherein said first MISFETs are formed on said recessed part of said major surface and said second MISFETs are formed on said projected part of said major surface, and further wherein an altitude difference between said recessed part and said projected part of said major surface is set to a predetermined value based upon a depth of focus of a predetermined exposure apparatus used for forming said first and second MISFETs so that predetermined areas of both said first and second MISFETs will be within said depth of focus of the predetermined exposure apparatus to permit simultaneous processing of said predetermined areas of said first and second MISFETs during formation of said first and second MISFETs.
2 more elements
A semiconductor integrated circuit device comprising:
- (a) a semiconductor substrate having a major surface which includes a recessed part and a projected part;
- (b) a first layer level of conductive film including first conductive strips arranged in said recessed part and said projected part;
- (c) a plurality of layer levels of conductive films formed between said recessed part of said major surface of said semiconductor substrate and said first layer level of conductive film, wherein at least one layer level of said plurality of layer levels of conductive films has second conductive strips formed only in said recessed part;
- and
- (d) a plurality of memory cells each having a MISFET and a capacitor element arranged in said recessed part.
2 more elements
A semiconductor integrated circuit device comprising:
- (a) a semiconductor substrate having a first portion and a second portion, said first portion having a first level of main surface and said second portion having a second level of main surface which is higher than said first level of said main surface;
- wherein
- each of the first portion and the second portion of the semiconductor substrate includes a p-type well region;
- (b) first conductive strips formed above the p-type well in said first portion, each of said first conductive strips having a third level, and second conductive strips formed above the p-type well in said second portion, each of said second conductive strips having a fourth level, wherein said first and second conductive strips are formed by patterning a first conductive film;
- and
- (c) third conductive strips formed over said first conductive strips above said p-type well in said first portion, each of said third conductive strips having a fifth level, and fourth conductive strips formed over said second conductive strips above said p-type well in said second portion, each of said fourth conductive strips having a sixth level, wherein said third and fourth conductive strips are formed by patterning a second conductive film,
- wherein a level difference between each of the third conductive strips and each of the first conductive strips is larger than a level difference between each of said fourth conductive strips and each of said second conductive strips.
4 more elements
A semiconductor memory having memory cells and a peripheral circuit comprising:
- (a) a semiconductor substrate having a major surface which includes a recessed part and a projected part;
- (b) first MISFETs each comprising a first gate electrode formed on said major surface of said semiconductor substrate and a first source region and a first drain region in said semiconductor substrate, and capacitor elements each comprising a first electrode connected to one of said first source region and said first drain region, a second electrode and a dielectric film therebetween, each of said memory cells including at least one of said first MISFETs and at least one of said capacitor elements;
- (c) second MISFETs each comprising a second gate electrode formed on said major surface of said semiconductor substrate and a second source region and a second drain region in said semiconductor substrate, said peripheral circuit including at least two of said second MISFETs;
- (d) a first insulating film formed on said first MISFETs, said capacitor elements and said second MISFETs;
- and
- (e) first conductive strips arranged on said first insulating film, wherein a first group of said first conductive strips extends over said capacitor elements and a second group of said first conductive strips electrically connects said second MISFETs to each other,
- wherein said first and second electrodes and dielectric film of each of said capacitor elements are formed over a corresponding first gate electrode of a corresponding one of said first MISFETs, and
- wherein said first MISFETs and capacitor elements of said memory cells are formed in said recessed part of said major surface and said second MISFETs of said peripheral circuit are formed in said projected part of said major surface.
5 more elements
A semiconductor memory having a memory cell and a peripheral circuit, comprising:
- (a) a semiconductor substrate having a major surface which includes a recessed part and a projected part;
- (b) a first MISFET comprising a first gate electrode formed over said major surface of said semiconductor substrate and a first source region and a first drain region of N-type conductivity formed in said semiconductor substrate, and a capacitor element comprising a first electrode connected to one of said first source region and said first drain region, and a second electrode and a dielectric film therebetween, said memory cell including said first MISFET and said capacitor element;
- (c) a second MISFET comprising a second gate electrode formed over said major surface of said semiconductor substrate and a second source region and a second drain region of N-type conductivity formed in said semiconductor substrate, and a third MISFET having a third gate electrode formed over said major surface of said semiconductor substrate and a third source region and a third drain region of p-type conductivity formed in said semiconductor substrate, said peripheral circuit including said second MISFET and said third MISFET;
- (d) a first insulating film formed over said first MISFET, said capacitor element, said second MISFET and said third MISFET;
- and
- (e) a first conductive strip and a second conductive strip arranged on said first insulating film, wherein said first conductive strip extends over said capacitor element and said second conductive strip electrically connects said second MISFET and said third MISFET,
- wherein said first and second electrodes and dielectric film of said capacitor element are formed over said first gate electrode of said first MISFET, and
- wherein said first MISFET and capacitor element of said memory cell are formed in said recessed part of said major surface and said second MISFET and said third MISFET of said peripheral circuit are formed in said projected part of said major surface.
5 more elements
Dependencies are inferred from the claim text.