Variable delay cell with hysteresis and ring oscillator using same

A variable frequency oscillator operatively controlled by a control signal (contr, contr′) comprising an odd number of cascaded inverting cells (14, 15, 16), a first inverting cell having an input connected to receive an input signal, each succeeding inverting cell of the cascaded inverting cells (14, 15, 16) having an input connected to receive an output signal (ext, ext′) derived from a preceding inverting cell, the output signal (ext, ext′) being connected to a control circuit (17, 18) having a control signal applied thereto for controlling a temporal profile of the output signal (ext, ext′), the input of the first inverting cell (16) being connected to receive an output of the last cell (15) of the cascaded inverting cells, at least one inverting cell (14, 15) being constituted by a cell having a gain that is variable as a function of the control signal (contr, contr′) applied to said at least one inverting cell (14, 15) for causing the output signal (ext ext′) from said at least one inverting cell (14, 15) to remain substantially in its current logic state for a certain length of time after which the output signal (ext, ext′) from said at least one inverting cell abruptly (14, 15) changes to a logic state with a steep leading edge at the output of said at least one inverting cell (14, 15) for a change in logic state at the input of said at least one inverting cell (14, 15).

A ring oscillator having a variable frequency controlled by an analog control signal, comprising an odd number of cascaded inverting gates,

• each inverting gate having an input connected to receive an input signal which, except for the first of the cascaded inverting gates, corresponds to an output signal derived from a preceding inverting gate, the input of the first inverting gate being connected to receive the output signal of the last inverting gate, and
• at least one inverting gate being constituted by a cell having a gain that is variable as a function of the analog control signal for causing the output signal to remain substantially in its current logic state for a certain length of time after which the output signal abruptly changes to a logic state with a steep leading edge at the output of said at least one inverting gate in response to predetermined steep edges at the input of said at least one inverting gate, the cell including:
• one inverter connected between a high-potential node and a low-potential node and having an input connected to receive said input signal and an output node providing said output signal,
• a first N-type transistor having a drain connected to said low-potential node, a source connected to a first fixed potential lower than the potential of said low-potential node, and a gate connected to receive the analog control signal, and
• a second N-type transistor having a drain connected to a second fixed potential equal or higher than the potential of said high-potential node, a source connected to said low-potential node and a gate connected to said output node.

A ring oscillator having a variable frequency controlled by an analog control signal, comprising an odd number of cascaded inverting gates,

• each inverting gate having an input connected to receive an input signal which, except for the first of the cascaded inverting gates, corresponds to an output signal derived from a preceding inverting gate, the input of the first inverting gate being connected to receive the output signal of the last inverting gate, and
• at least one inverting gate being constituted by a cell having a gain that is variable as a function of the analog control signal for causing the output signal to remain substantially in its current logic state for a certain length of time after which the output signal abruptly changes to a logic state with a steep leading edge at the output of said at least one inverting gate in response to predetermined steep edges at the input of said at least one inverting gate, the cell including:
• one inverted connected between a high-potential node and a low-potential node and having an input connected to receive said input signal and an output node providing said output signal,
• a first P-type transistor having a drain connected to said high-potential node, a source connected to a first fixed potential higher than the potential of said high-potential node and a gate connected to receive the analog control signal, and
• a second P-type transistor having a drain connected to a fixed potential equal to or lower than the potential of said low-potential node, a source connected to said high-potential node and a gate connected to said output node.

A ring oscillator having a variable frequency controlled by an analog control signal in digital form having bits, comprising an odd number of cascaded inverting gates,

• each inverting gate having an input connected to receive an input signal which, except for the first of the cascaded inverting gates, corresponds to an output signal derived from a preceding inverting gate, the input of the first inverting gate being connected to receive the output signal of the last inverting gate, and
• at least one inverting gate being constituted by a cell having a gain that is variable as a function of the digital control signal for causing the output signal to remain substantially in its current logic state for a certain length of time after which the output signal abruptly changes to a logic state with a steep leading edge at the output of said at least one inverting gate in response to predetermined steep edges at the input of said at least one inverting gate, the cell including:
• one inverter connected between a high-potential node and a low-potential node and having an input connected to receive said input signal and an output node providing said output signal,
• a plurality of first N-type transistors having drains connected to said low-potential node, sources connected to a first fixed potential lower than the potential of said low-potential node, and gates connected to receive the respective bits of the digital control signal, and
• a second N-type transistor having a drain connected to a second fixed potential equal or higher than the potential of said high-potential node, a source connected to said low-potential node and a gate connected to said output node.

A ring oscillator having a variable frequency controlled by a digital control signal in digital form having bits, comprising an odd number of cascaded inverting gates, each inverting gate having an input connected to receive an input signal which, except

• for the first of the cascaded inverting gates, corresponds to an output signal derived from a preceding inverting gate, the input of the first inverting gate being connected to receive the output signal of the last inverting gate, and
• at least one inverting gate being constituted by a cell having a gain that is variable as a function of the digital control signal for causing the output signal to remain substantially in its current logic state for a certain length of time after which the output signal abruptly changes to a logic state with a steep leading edge at the output of said at least one inverting gate in response to predetermined steep edges at the input of said at least one inverting gate, the cell including:
• one inverter connected between a high-potential node and a low-potential node and having an input connected to receive said input signal and an output node providing said output signal,
• a plurality of first P-type transistors having drains connected to said high-potential node, sources connected to a fixed potential higher than the potential of said high-potential node and gates connected to receive the respective bits of the digital control signal, and
• a second P-type transistor having a drain connected to a fixed potential equal or lower than the potential of said low-potential node, a source connected to said high-potential node and a gate connected to said output node.

A variable delay cell comprising:

• an input for receiving an input signal,
• an output for providing an output signal with a variable delay in response to said input signal,
• a gain variable as a function of an analog control signal for causing the output signal to remain substantially in its current logic state for a certain length of time after which the output signal abruptly changes to a logic state with a steep leading edge at the output of the cell in response to predetermined steep edges of said input signal,
• one inverter connected between a high-potential node and a low-potential node and having an input connected to said input of the cell and an output node providing said output signal,
• a first N-type transistor having a drain connected to said low-potential node, a source connected to a first fixed potential lower than the potential of said low-potential node, and a gate connected to receive the analog control signal, and
• a second N-type transistor having a drain connected to a second fixed potential equal or higher than the potential of said high-potential node, a source connected to said low-potential node and a gate connected to said output node.

A variable delay cell comprising:

• an input for receiving an input signal,
• an output for providing an output signal with a variable delay in response to said input signal,
• a gain variable as a function of an analog control signal for causing the output signal to remain substantially in its current logic state for a certain length of time after which the output signal abruptly changes to a logic state with a steep leading edge at the output of the cell in response to predetermined steep edges of said input signal,
• one inverter connected between a high-potential node and a low-potential node and having an input connected to said input of the cell and an output node providing said output signal,
• a first P-type transistor having a drain connected to said high-potential node, a source connected to a fixed potential higher than the potential of said high-potential node and a gate connected to receive said analog control signal, and
• a second P-type transistor having a drain connected to a fixed potential equal to or lower than the potential of said low-potential node, a source connected to said high-potential node and a gate connected to said output node.

A variable delay cell, comprising:

• an input for receiving an input signal,
• an output for providing an output signal with a variable delay in response to said input signal,
• a gain variable as a function of a digital control signal for causing the output signal to remain substantially in its current logic state for a certain length of time after which the output signal abruptly changes to a logic state with a steep leading edge at the output of the cell in response to predetermined steep edges of said input signal, said digital control signal having bits,
• one inverter connected between a high-potential node and a low-potential node and having an input connected to receive said input signal and an output node providing said output signal,
• a plurality of first N-type transistors having drains connected to said low-potential node, sources connected to a first fixed potential lower than the potential of said low-potential node, and gates connected to receive the respective bits of the digital control signal, and
• a second N-type transistor having a drain connected to a second fixed potential equal or higher than the potential of said high-potential node, a source connected to said low-potential node and a gate connected to said output node.

A variable delay cell comprising:

• an input for receiving an input signal,
• an output for providing an output signal with a variable delay in response to said input signal,
• a gain variable as a function of a digital control signal for causing the output signal to remain substantially in its current logic state for a certain length of time after which the output signal abruptly changes to a logic state with a steep leading edge at the output of the cell in response to predetermined steep edges of said input signal, said digital control signal having bits,
• one inverter connected between a high-potential node and a low-potential node and having an input connected to receive said input signal and an output node providing said output signal,
• a plurality of first P-type transistors having drains connected to said high-potential node, sources connected to a fixed potential higher than the potential of said high-potential node and gates connected to receive the respective bits of the digital control signal, and
• a second P-type transistor having a drain connected to a fixed potential equal to or lower than the potential of said low-potential node, a source connected to said high-potential node and a gate connected to said output node.