US RE38,222 E1 · Electrostatic discharge protection circuit triggered by capacitive-coupling

Abstract

An electrostatic discharge (ESD) protection circuit connected to an integrated circuit pad for protecting an internal circuit from ESD damage. The ESD protection circuit includes an NMOS/PMOS transistor, a capacitor, and a load The NMOS/PMOS is configured with a drain connected to the IC pad and a source for connection to the circuit VSS/VDD. Agate of the NMOS/PMOS transistor is tied to the source. The capacitor is connected between the IC pad and the bulk of the NMOS/PMOS transistor The load, which is either another NMOS/PMOS transistor or a resistor, is to be connected between the VSS/VDD and the bulk of the NMOS/PMOS transistor. In accordance with the invention, the NMOS/PMOS transistor is fabricated in a P-well/N-well region of a semiconductor substrate. The capacitor includes an IC pad and a polysilicon layer therebelow, with an intervening dielectric layer.

Claims22

Dependent claims

An electrostatic discharge protection circuit for protecting an internal circuit, comprising:

an N-type semiconductor substrate;
a P-well region in the substrate;
a contact region in the P-well region;
an isolating structure on the substrate;
a conducting layer on the isolating structure, coupled to the contact region;
a dielectric lays overlying the conducting layer;
a metal pad on the dielectric layer, wherein the metal pad, the dielectric layer, and the conducting layer form a capacitor for coupling ESD voltage to the P-well region when an ESD stress is present at the pad;
a first N-type heavily-doped region in the P-well region, coupled to the pad;
a second N-type heavily-doped region for coupling to a circuit ground of the internal circuit, the second N-type heavily doped region being disposed in the P-well region, spaced apart from and electrically isolated from the first N-type heavily-doped region;
a gate structure, disposed on the P-well region between the first N-type heavily-doped region and the second N-type heavily-doped region, for connection to the circuit ground, wherein the first N-type heavily-doped region, the second N-type heavily-doped region, the gate structure, and the P-well region form an NMOS transistor which bypasses ESD stress when an ESD voltage is coupled to the P-well region through the capacitor;
and
a load connected between the contact region and the circuit ground when the gate structure and the second N-type heavily doped region are connected to the circuit ground, for coupling the P-well region of the NMOS transistor to the circuit ground.

9 more elements

An electrostatic discharge protection circuit for coupling to a power rail, comprising:

a P-type semiconductor substrate;
an N-well region in the substrate;
a contact region in the N-well region;
an isolating someone on the substrate;
a conducing layer on the isolating structure, coupled to the contact region;
a dielectric layer overlying the conducting layer;
a metal pad on the dielectric layer, wherein the metal pad the dielectric layer, and the conducting layer form a capacitor for coupling ESD voltage to the N-well region when an ESD stress is present at the pad;
a first P-type heavily-doped region is the N-well region, coupled to the pad;
a second P-type heavily-doped region in the N-web region, spaced apart from and electrically isolated from the first P-type heavily-doped region, for coupling to the power rail:
a gate structure, formed on the N-well region between the first P-type heavily-doped region and the second P-type heavily-doped region, for correction to the power rail, wherein the first P-type heavily-doped region, the second P-type heavily-doped region, the gate structure, and the N-well region form a PMOS transistor which bypasses ESD stress when an ESD voltage is coupled to the N-well region through the capacitor;
and
a load connected between the contact region and the power rail when the gate structure is connected to the power rail, for coupling the N-well region of the PMOS transistor to the power rail.

9 more elements

Dependencies are inferred from the claim text.

Electrostatic discharge protection circuit triggered by capacitive-coupling

Life of this patent

Electrostatic discharge protection circuit triggered by capacitive-coupling

Life of this patent

Abstract

Claims22