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US RE38,154 E1Granted
Method and circuit for detecting a fault in a clock signal for microprocessor electronic devices including memory elements
AssigneeSTMicroelectronics S.r.l.
InventorsAngelo Moroni, Flavio Scarra, Alberto Taddeo
Life of this patent
Estimating the term…
Abstract
An electronic device including a microprocessor, a circuit generating a clock signal, and memories of both the volatile type and the non-volatile type, incorporates a circuit for generation of a reset signal capable of detecting a stop in the oscillation of said clock signal and generating a logic signal coupled with the reset input of the microprocessor. The circuit monitors the clock signal applied to the device and, if an irregularity is detected, generate a reset signal holding the microprocessor in a safe state. The reset signal is held until the circuit generating the clock signal resumes normal operation.
Claims38
A non-volatile electrically programmable and erasable memory device including a memory cell matrix and a microprocessor interlocked with a circuit generating at least one oscillating periodic clock signal, comprising:
- a circuit for generation of a reset signal for said microprocessor having an input terminal coupled with an output of the circuit generating at least one oscillating clock signal and an output terminal coupled with a reset input of the microprocessor;
- wherein said circuit for generating of a reset signal detects a stop in the oscillation of said clock signal and generates the reset signal in response to detecting the stop in the oscillation of said clock signal.
A clock detector, comprising:
- a detector input terminal operable to receive a clock signal;
- a detector output terminal;
- and
- a circuit coupled to the detector input and output terminals and operable to generate a first signal on the detector output terminal if the clock signal has a first predetermined characteristic and operable to generate a second signal on the detector output terminal if the clock signal has a second predetermined characteristic, the circuit comprising,
- a first stage operable to generate a third signal in response to the clock signal,
- a second stage operable to generate a fourth signal in response to the clock signal, and
- a third stage coupled to the first and second stages and operable to generate the first signal if the third and fourth signals are equal and operable to generate the second signal if the third and fourth signals are unequal.
4 more elements
A clock detector, comprising:
- a detector input terminal operable to receive a clock signal;
- a detector output terminal;
- and
- a circuit coupled to the detector input and output terminals and operable to generate a first signal on the detector output terminal if the clock signal has a first predetermined characteristic and operable to generate a second signal on the detector output terminal if the clock signal has a second predetermined characteristic, the circuit comprising,
- a first inverter operable to generate a third signal in response to the clock signal,
- a second inverter operable to generate a fourth signal in response to the clock signal, and
- a logic gate coupled to the first and second stages and operable to generate the first signal if the third and fourth signals are equal and operable to generate the second signal if the third and fourth signals are unequal.
4 more elements
A clock detector, comprising:
- a detector input terminal operable to receive a clock signal;
- a detector output terminal;
- and
- a circuit coupled to the detector input and output terminals and operable to generate a first signal on the detector output terminal if the clock signal has a first predetermined characteristic and operable to generate a second signal on the detector output terminal if the clock signal has a second predetermined characteristic, the circuit comprising,
- a first inverter having an input terminal coupled to the detector input terminal and having an output terminal,
- a first capacitor coupled to the output terminal of the first inverter,
- a second inverter having an input terminal coupled to the detector input terminal and having an output terminal,
- a second capacitor coupled to the output terminal of the second inverter, and
- a logic gate having first and second input terminals respectively coupled to the output terminals of the first and second inverters and having an output terminal coupled to the detector output terminal.
6 more elements
A clock detector, comprising:
- a detector input terminal operable to receive a clock signal;
- a detector output terminal;
- and
- a circuit coupled to the detector input and output terminals and operable to generate a first signal on the detector output terminal if the clock signal has a first predetermined characteristic and operable to generate a second signal on the detector output terminal if the clock signal has a second predetermined characteristic, the circuit comprising,
- a first inverter having an input terminal and an output terminal,
- a first capacitor coupled to the output terminal of the first inverter,
- a second inverter having an input terminal coupled to the detector input terminal and having an output terminal,
- a second capacitor coupled to the output terminal of the second inverter,
- a third inverter having an input terminal coupled to the detector input terminal and having an output terminal coupled to the input terminal of the first inverter, and
- a logic gate having first and second input terminals respectively coupled to the output terminals of the first and second inverters and having an output terminal coupled to the detector output terminal.
7 more elements
A circuit comprising:
- a functional circuit operable to receive a clock signal and a supply signal;
- and
- a control circuit coupled to the functional circuit and operable to receive the clock and supply signals, to allow the functional circuit to operate if the clock signal has a first predetermined characteristic and the supply signal has a first predetermined relationship to a predetermined threshold, and to reset the functional circuit if the clock signal has a second predetermined characteristic or if the supply signal has a second predetermined relationship to the predetermined threshold.
A circuit, comprising:
- a functional circuit operable to receive a clock signal, a supply signal, and a reset signal;
- a reset circuit coupled to the functional circuit and operable to generate the reset signal;
- and
- a control circuit coupled to the reset circuit and operable to receive the clock signal and the supply signal, the control signal operable to cause the reset circuit to generate the reset signal if the clock signal has a predetermined characteristic or if the supply signal has a predetermined relationship to a predetermined threshold.
1 more element
A circuit comprising:
- a memory circuit operable to store data;
- a reset circuit operable to generate a reset signal;
- a control circuit coupled to the reset circuit, operable to receive a clock signal, and operable to cause the reset circuit to generate the reset signal if the clock signal has a predetermined characteristic;
- and
- a processor coupled to the memory circuit and to the reset circuit, the processor operable to receive the clock signal and, in response to the reset signal, being unable to alter the data stored in the memory circuit.
2 more elements
A method comprising:
- allowing a functional circuit to operate if a clock signal coupled to the functional circuit has a first predetermined characteristic and if a supply signal coupled to the functional circuit has a first predetermined relationship to a predetermined threshold;
- and
- resetting the functional circuit if the clock signal has a second predetermined characteristic or if the supply signal has a second predetermined relationship to the predetermined threshold.
A method, comprising:
- determining whether a clock signal has a predetermined characteristic;
- determining whether a supply signal has a predetermined relationship to a predetermined threshold value;
- and
- resetting a circuit if the clock signal has the predetermined characteristic or if the supply signal has the predetermined relationship.
1 more element
A method, comprising:
- receiving a clock signal;
- generating a reset signal if the clock signal has a predetermined characteristic;
- and
- resetting a processor with the reset signal to prevent the processor from altering data stored in a memory circuit.
1 more element
Dependencies are inferred from the claim text.