Block write circuit and method for wide data path memory device

A block write circuit in a memory device including at least one array of memory cells, each of the at least one array of memory cells including a plurality of memory cells arranged in rows and columns and a plurality of digit lines, each digit line coupled to a plurality of memory cells in an associated column, the block write circuit comprising:

• a plurality of input/output lines;
• a switch circuit coupled between the input/output lines and the digit lines, the switch circuit selectively coupling at least one digit line to each input/output line responsive to an address signal during a block write mode of operation;
• a plurality of driver circuits, each driver circuit including an input, and an output coupled to a respective input/output lines, and developing a data signal on its output in response to a data signal applied on its input;
• and
• a multiplexer circuit having an input adapted to receive a data signal, and a plurality of outputs coupled to respective inputs of the driver circuits, the multiplexer circuit coupling its input to selected ones of its outputs and isolating its input from the other ones of its outputs responsive to first signals during the block write mode of operation.

A block write circuit in a memory device, comprising:

• a plurality of data terminals adapted to receive respective data signals;
• a plurality of arrays groups, each array group including a plurality of arrays and each array including a plurality of memory cells arranged in rows and columns and a plurality of digit lines, each digit line coupled to a plurality of memory cells in an associated column;
• a plurality of input/output line groups, each input/output line group including a plurality of input/output lines;
• a plurality of switch circuits, each switch circuit coupled between the input/output lines of a respective input/output line group and the digit lines of the arrays in an associated array group, and each switch circuit selectively coupling at least one digit line to each input/output line responsive to address signals during a block write mode of operation;
• a plurality of write driver groups, each write driver group including a plurality of write driver circuits having outputs coupled to respective input/output lines in an associated input/output line group, each write driver circuit including an input, and developing a data signal on its output responsive to a data signal applied on its input;
• and
• a multiplexer circuit including a plurality of inputs coupled to respective data terminals, and a plurality of output subgroups, each output subgroup associated with a respective input, and each output group including a plurality of outputs coupled to respective inputs of the write driver circuits in an associated write driver group, the multiplexer circuit operable responsive to the control signal in a block write mode to couple each of its inputs to the outputs in the associated output subgroup.

A block write circuit in a memory device including a plurality of data terminals and an array including a plurality of memory cells arranged in rows and columns and having a plurality of digit lines, each digit line coupled to a plurality of memory cells in an associated column, the block write circuit comprising:

• a plurality of input/output lines;
• a switch circuit coupled between the input/output lines and the digit lines, the switch circuit selectively coupling at least one digit line to each input/output line responsive to an address signal during a block write mode of operation;
• a plurality of write driver circuits, each write driver circuit having an input, an output coupled to a respective input/output line, and developing a data signal on its output in response to a data signal applied on its input;
• a plurality of buffer circuits, each buffer circuit including an output, an input coupled to a respective data terminal, and an enable terminal adapted to receive an enable signal, each buffer circuit developing a signal on its output in response to a signal applied on its input when the enable signal is active, and placing its output in a high impedance state when the enable signal is inactive;
• a masking circuit adapted to receive a plurality of masking signals, and applying a plurality of enable signals to respective enable terminals of the buffer circuits in response to the masking signals;
• and
• a multiplexer circuit having a plurality of inputs coupled to respective outputs of the buffer circuits, and a plurality of outputs coupled to respective inputs of the write driver circuits, the multiplexer circuit operable responsive to a control signal in the block write mode to couple each of its inputs to a plurality of associated outputs.

A memory device, comprising:

• an address bus adapted to receive address signals;
• a control bus adapted to receive control signals;
• a data bus adapted to receive at least one data signal;
• at least one array of memory cells including a plurality of memory cells arranged in rows and columns and a plurality of digit lines, each digit line coupled to the memory cells in associated column;
• an address decoder coupled to the address bus and the at least one array;
• a control circuit coupled to the control bus;
• a read/write circuit coupled to the data bus;
• and
• a block write circuit coupled to the address decoder and control circuit, the block write circuit comprising:
• a plurality of input/output lines;
• a switch circuit coupled between the input/output lines and the digit lines of the at least one array, the switch circuit selectively coupling at least one digit line to each input/output line responsive to an address signal during a block write mode of operation;
• a plurality of driver circuits, each driver circuit including an input, and an output coupled to a respective input/output line, and developing a data signal on its output in response to a data signal applied on its input;
• and
• a multiplexer circuit having an input adapted to receive a data signal, and a plurality of outputs coupled to respective inputs of the driver circuits, the multiplexer circuit coupling its input to its outputs responsive to a control signal during the block write mode of operation.

A memory device, comprising:

• an address bus adapted to receive address signals;
• a control bus adapted to receive control signals;
• a data bus adapted to receive at least one data signal;
• at least one array of memory cells including a plurality of memory cells arranged in rows and columns and a plurality of digit lines, each digit line coupled to the memory cells in associated column;
• an address decoder coupled to the address bus and the at least one array;
• a control circuit coupled to the control bus;
• a read/write circuit coupled to the data bus;
• and
• a block write circuit coupled to the address decoder and control circuit, the block write circuit comprising:
• a plurality of input/output lines;
• a switch circuit coupled between the input/output lines and the digit lines of the at least one array, the switch circuit selectively coupling at least one digit line to each input/output line responsive to an address signal during a block write mode of operation;
• a plurality of driver circuits, each driver circuit including an input, and an output coupled to a respective input/output line, and developing a data signal on its output in response to a data signal applied on its input;
• a plurality of buffer circuits, each buffer circuit including an output, an input coupled to a respective data terminal of the data bus, and an enable terminal adapted to receive an enable signal, each buffer circuit developing a signal on its output in response to a signal applied on its input when the enable signal is active, and placing its output in a high impedance state when the enable signal is inactive;
• a masking circuit coupled to the data bus and adapted to receive a plurality of masking signals and applying a plurality of enable signals to respective enable terminals of the buffer circuits in response to the masking signals;
• a multiplexer circuit having a plurality of inputs coupled to respective outputs of the buffer circuits, and a plurality of outputs coupled to respective inputs of the write driver circuits, the multiplexer circuit operable responsive to a control signal to couple each of its inputs to a plurality of associated outputs in the block write mode;
• and
• a color register coupled to the data bus and to the inputs of the multiplexer circuit, the color register operable to store color data bits applied on the data bus and apply color data bits to the inputs of the multiplexer circuit during the block write mode.

An embedded memory device, comprising:

• a logic circuit developing address, and control signals on respective internal address, data and control busses, and operable to perform a desired function;
• and
• a memory device coupled to the logic circuit through the internal address, control, and data busses, the memory device comprising:
• an address bus adapted to receive address signals;
• a control bus adapted to receive control signals;
• a data bus adapted to receive at least one data signal;
• at least one array of memory cells including a plurality of memory cells arranged in rows and columns and a plurality of digit lines, each digit line coupled to the memory cells in an associated column;
• an address decoder coupled to the address bus and the at least one array;
• a control circuit coupled to the control bus;
• a read/write circuit coupled to the data bus;
• and
• a block write circuit coupled to the address decoder and control circuit, the block write circuit comprising:
• a plurality of input/output lines;
• a switch circuit coupled between the input/output lines and the digit lines of the at least one array, the switch circuit selectively coupling at least one digit line to each input/output line responsive to an address signal during a block write mode of operation;
• a plurality of driver circuits, each driver circuit including an input, and an output coupled to a respective input/output line, and developing a data signal on its output in response to a data signal applied on its input;
• and
• a multiplexer circuit having an input adapted to receive a data signal, and a plurality of outputs coupled to respective inputs of the driver circuits, the multiplexer circuit coupling its input to its outputs responsive to a control signal during the block write mode of operation.

A computer system, comprising:

• a data input device;
• a data output device;
• and
• computing circuitry coupled to the data input and output devices, the computing circuitry including an embedded memory device, comprising:
• a logic circuit operable to perform a desired function, and operable to develop address, data, and control signals on respective internal address, data and control busses;
• and
• a memory device coupled to the logic circuit through the internal address, control, and data busses, the memory device comprising:
• an address bus adapted to receive address signals;
• a control bus adapted to receive control signals;
• a data bus adapted to receive at least one data signal;
• at least one array of memory cells including a plurality of memory cells arranged in rows and columns and a plurality of digit lines, each digit line coupled to the memory cells in an associated column;
• an address decoder coupled to the address bus and the at least one array;
• a control circuit coupled to the control bus;
• a read/write circuit coupled to the data bus;
• and
• a block write circuit coupled to the address decoder and control circuit, the block write circuit comprising:
• a plurality of input/output lines;
• a switch circuit coupled between the input/output lines and the digit lines of the at least one array, the switch circuit selectively coupling at least one digit line to each input/output line responsive to an address signal during a block write mode of operation;
• a plurality of driver circuits, each driver circuit including an input, and an output coupled to a respective input/output line, and developing a data signal on its output in response to a data signal applied on its input;
• and
• a multiplexer circuit having an input adapted to receive a data signal, and a plurality of outputs coupled to respective inputs of the driver circuits, the multiplexer circuit coupling its input to its outputs responsive to a control signal during the block write mode of operation.

A method for writing a block of data to a plurality of memory cells in a memory device including a data terminal and having an array of memry cells, the array including a plurality of memory cells arranged in rows and columns and a plurality of digit lines, each digit line coupled to the digit lines in an associated column, and a plurality of input/output lines being coupled through a switch circuit to the digit lines, comprising:

• activating a row of memory cells in the array;
• coupling the digit lines associated with an addressed block of memory cells to respective input/output lines, each digit line being coupled to a different input/output line;
• and
• transferring a data signal applied on the data terminal over the respective input/output lines and over the corresponding digit lines to each of the memory cells in the addressed block.

A method for writing a block of data to a plurality of memory cells in a memory device including a data terminal and having an array of memory cells, the array including a plurality of memory cells arranged in rows and columns and a plurality of digit lines, each digit line coupled to the digit lines in an associated column, and a plurality of input/output lines being coupled through a switch circuit to the digit lines, comprising:

• activating a row of memory cells in the array;
• coupling the digit lines associated with an addressed block of memory cells to respective input/output lines, each digit line being coupled to a different input/output line;
• and
• transferring a data signal applied on the data terminal over the respective input/output lines and over the corresponding digit lines to each of the memory cells in the addressed block;
• and
• isolating the data signal from selected input/output lines to thereby mask the data signal from corresponding memory cells in the addressed block.

A method for writing a block of data to a plurality of memory cells in a memory device including a data terminal and having an array of memory cells, the array including a plurality of memory cells arranged in rows and columns and a plurality of digit lines, each digit line coupled to the digit lines in an associated column, and a plurality of input/output lines being coupled through a switch circuit to the digit lines, comprising:

• activating a plurality of memory cells in the array;
• placing the memory device in a block write mode;
• coupling at least some of the activated memory cells through the associated digit lines to respective input/output lines;
• and
• transferring a data signal applied on the data terminal over respective input/output lines to memory cells coupled to the input/output lines.

A block write circuit in a memory device including at least one array of memory cells, each of the at least one array of memory cells including a plurality of memory cells arranged in rows and columns and a plurality of digit lines, each digit line coupled to a plurality of memory cells in an associated column, the block write circuit comprising:

• a plurality of input/output lines;
• a switch circuit coupled between the input/output lines and the digit lines, the switch circuit selectively coupling at least one digit line to each input/output line responsive to an address signal during a block write mode of operation;
• a plurality of driver circuits, each driver circuit including an input, an output coupled to a respective input/output line, and developing a data signal on its output in response to a data signal applied on its input;
• a plurality of buffer circuits, each buffer circuit including an output, an input coupled to a respective data terminal, and an enable terminal adapted to receive an enable signal, each buffer circuit developing a signal on its output in response to a signal applied on its input when the enable signal is active, and placing its output in a high impedance state when the enable signal is inactive;
• a masking circuit adapted to receive a plurality of masking signals, and applying a plurality of enable signals to respective enable terminals of the buffer circuits in response to the masking signals;
• and
• a multiplexer circuit having an input adapted to receive a data signal, a control terminal adapted to receive a control signal, and a plurality of outputs coupled to respective inputs of the driver circuits, the multiplexer circuit coupling the input to selected outputs responsive to the control signal during the block write mode of operation.

A block write circuit in a memory device, comprising:

• a plurality of data terminals adapted to receive respective data signals;
• a plurality of array groups, each array group including a plurality of arrays and each array including a plurality of memory cells arranged in rows and columns and a plurality of digit lines, each digit line coupled to a plurality of memory cells in an associated column;
• a plurality of input/output line groups, each input/output line group including a plurality of input/output lines;
• a plurality of switch circuits, each switch circuit coupled between the input/output lines of a respective input/output line group and the digit lines of the arrays in an associated array group, and each switch circuit selectively coupling at least one digit line to each input/output line responsive to address signals during a block write mode of operation;
• a plurality of write driver groups, each write driver group including a plurality of write driver circuits having outputs coupled to respective input/output lines in an associated input/output line group, each write driver circuit including an input, and developing a data signal on its output responsive to a data signal applied on its input;
• a plurality of buffer circuits, each buffer circuit including an output, an input coupled to a respective data terminal, and an enable terminal adapted to receive an enable signal, each buffer circuit developing a signal on its output in response to a signal applied on its input when the enable signal is active, and placing its output in a high impedance state when the enable signal is inactive;
• a masking circuit adapted to receive a plurality of masking signals, and applying a plurality of enable signals to respective enable terminals of the buffer circuits in response to the masking signals;
• and
• a multiplexer circuit including a plurality of inputs coupled to respective outputs of the buffer circuits and including a plurality of output subgroups, each output subgroup, associated with a respective input, and each output group including a plurality of outputs coupled to respective inputs of the write driver circuits in an associated write driver group, the multiplexer circuit operable responsive to the control signal in a block write mode to couple each of its input to the outputs in the associated output subgroup.

A memory device, comprising:

• an address bus adapted to receive address signals;
• a control bus adapted to receive control signals;
• a data bus adapted to receive at least one data signal;
• at least one array of memory cells including a plurality of memory cells arranged in rows and columns and a plurality of digit lines, each digit line coupled to the memory cells in an associated column;
• an address decoder coupled to the address bus and the at least one array;
• a control circuit coupled to the control bus;
• a read/write circuit coupled to the data bus;
• and
• a block write circuit coupled to the address decoder and control circuit, the block write comprising:
• a plurality of input/output lines;
• a switch circuit coupled between the input/output lines and the digit lines of the at least one array, the switch circuit selectively coupling at least one digit line to each input/output line responsive to an address signal during a block write mode of operation;
• a plurality of driver circuits, each driver circuit including an input, and an output coupled to a respective input/output line, and developing a data signal on its output in response to a data signal applied on its input;
• a plurality of buffer circuits, each buffer circuit including an output, an input coupled to a respective data terminal, and an enable terminal adapted to receive an enable signal, each buffer circuit developing a signal on its output in response to a signal applied on its input when the enable signal is active, and placing its output in a high impedance state when the enable signal is inactive;
• a masking circuit adapted to receive a plurality of masking signals, and applying a plurality of enable signals to respective enable terminals of the buffer circuits in response to the masking signals;
• and
• a multiplexer circuit having an input adapted to receive a data signal, a control terminal adapted to receive a control signal, and a plurality of outputs connected to respective inputs of the driver circuits, the multiplexer circuit coupling the input to selected outputs respective to the control signal during the block write mode of operation.

A method for writing a block of data to a plurality of memory cells in a memory device including a data terminal and having an array of memory cells, the array including a plurality of memory cells arranged in rows and columns and a plurality of digit lines, each digit line being coupled to the memory cells in an associated column, and the memory device including a plurality of input/output lines, the method comprising:

• activating a row of memory cells in the array;
• coupling the digit lines associated with an addressed block of memory cells to respective input/output lines, each digit line being coupled to a different input/output line;
• storing a masking bit in the memory device;
• transferring a data signal applied on the data terminal over the respective input/output lines and over the corresponding digit lines to each of the memory cells in the addressed block when the stored masking bit has a first value;
• and
• masking the data signal from the memory cells in the addressed block when the stored masking bit has a second value.

A block write circuit in a memory device including at least one array of memory cells, each of the at least one array of memory cells including a plurality of memory cells arranged in rows and columns and a plurality of digit lines, each digit line coupled to a plurality of memory cells in an associated column, the block write circuit comprising:

• a plurality of input/output lines;
• a switching means coupled between the input/output lines and the digit lines for selectively coupling at least one digit line to each input/output line responsive to an address signal during a block write mode of operation;
• a plurality of driver means each being coupled to respective input/output lines for developing a data signal on an output in response to a data signal applied on an input;
• a plurality of buffering means each being coupled to a respective data terminal for developing a signal on an output in response to a signal applied on an input when an applied enable signal is active, and for placing the output in a high impedance state when the enable signal is inactive;
• a masking means for applying a plurality of enable signals to respective enable terminals of the buffer circuits in response to a plurality of masking signals;
• and
• a multiplexing means having a plurality of outputs coupled to respective inputs of the driver means for coupling an input to a selected output responsive to a control signal during the block write mode of operation.