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US RE37,427 E1Granted
Dynamic type memory
AssigneeKabushiki Kaisha Toshiba
InventorsMasaki Ogihara, Satoru Takase, Kiyofumi Sakurai
Life of this patent
Estimating the term…
Abstract
In a dynamic type memory, a memory cell array is divided into a plurality of sub arrays on a memory chip. Each of the sub arrays is provided with a data line formed in parallel with word lines. Data buffer and multiplexer circuits and I/O pads are arranged on one side of the memory chip in parallel with bit lines. This arrangement allows a data path to be shortened and enables data to be transferred at high speed.
Claims120
A dynamic type memory comprising:
- a memory cell array formed on a semiconductor chip having a first edge and a second edge perpendicular to the first edge;
- a plurality of sub arrays into which said memory cell array is divided, said plurality of sub arrays being arranged in a first direction parallel to the first edge and a second direction perpendicular to said first direction, and grouped into a plurality of banks, each of said plurality of sub arrays having a plurality of memory cells arranged in matrix;
- a plurality of word lines formed on the semiconductor memory chip for each of said plurality of sub arrays and extending in the first direction, each of said plurality of word lines being connected to those of the memory cells which are in a row;
- a plurality of bit lines formed on the semiconductor memory chip for each of said plurality of sub arrays and extending in the second direction, each of said plurality of bit lines being connected to those of the memory cells which are in a column;
- a plurality of sense amplifiers formed on the semiconductor memory chip for each of said plurality of sub arrays and connected to said plurality of bit lines, each for sensing and amplifying a potential read out from a memory cell when a corresponding bit line is selected;
- a plurality of data lines formed on the semiconductor memory chip for said plurality of sub arrays and extending in the first direction in which said word lines extend, each of said plurality of data lines being connected to the sense amplifiers of a corresponding sub array, for transferring data sensed and amplified by a sense amplifier the bit line connected to which is selected;
- a plurality of data buffer and multiplexer circuits formed on the semiconductor memory chip in the second direction and in parallel to said second edge of said semiconductor memory chin chip, each of said plurality of data buffer and multiplexer circuits being connected to one of said sub arrays of each of said banks;
- and
- a plurality of input/output pads connected to said data buffer and multiplexer circuits, the input/output pads being in an arrangement in the second direction on the semiconductor memory chip and being in parallel to said second edge of said semiconductor memory, chip, the arrangement being closer to the second edge of the semiconductor memory chip than said data buffer and multiplexer circuits.
6 more elements
A semiconductor memory device, comprising:
- a semiconductor chip formed on a semiconductor substrate;
- a memory cell array formed on said semiconductor chip, said memory cell array comprising sub arrays organized into memory banks which are spaced apart from each other in one of a first and a second direction;
- data buffer and multiplexer circuits formed on said semiconductor chip and spaced apart from each other in the second direction, each data buffer and multiplexer circuit being connected to a sub array from each memory cell bank;
- and
- input/output pads formed on said semiconductor chip and spaced apart from each other in the second direction, each input/output pad being connected to a corresponding data buffer and multiplexer circuit,
- wherein said data buffer and multiplexer circuits are arranged between said input/output pads and said sub arrays.
3 more elements
A semiconductor memory device, comprising:
- a semiconductor chip formed on a semiconductor substrate;
- a memory cell array formed on said semiconductor chip, said memory cell array comprising sub arrays organized into memory banks which are spaced apart from each other in one of a first and a second direction, each sub array comprising memory cells arranged in rows and columns;
- word lines extending in the first direction and provided for each sub array, each word line connecting memory cells in a row of the corresponding sub array;
- bit lines extending in the second direction and provided for each sub array, each bit line connecting memory cells in a column of the corresponding sub array;
- data buffer and multiplexer circuits formed on said semiconductor chip and spaced apart from each other in the second direction;
- data lines including at least data line potions extending in the first direction and connecting said sub arrays and said data buffer and multiplexer circuits such that each data buffer and multiplexer circuit is connected to a sub array from each memory cell bank;
- and
- input/output pads formed on said semiconductor chip and spaced apart from each other in the second direction, each input/output pad being connected to a corresponding data buffer and multiplexer circuit,
- wherein said data buffer and multiplexer circuits are arranged between said input/output pads and said sub arrays.
6 more elements
A dynamic type memory comprising:
- a memory cell array formed on a semiconductor chip having a first edge and a second edge perpendicular to the first edge;
- a plurality of sub arrays into which said memory cell array is divided, said plurality of sub arrays being arranged in a first direction parallel to the first edge and a second direction perpendicular to said first direction, and grouped into a plurality of banks, each of said plurality of sub arrays having a plurality of memory cells arranged in matrix;
- a plurality of word lines formed on the semiconductor memory chip for each of said plurality of sub arrays and extending in the first direction, each of said plurality of word lines being connected to those of the memory cells which are in a row;
- a plurality of bit lines formed on the semiconductor memory chip for each of said plurality of sub arrays and extending in the second direction, each of said plurality of bit lines being connected to those of the memory cells which are in a column;
- a plurality of sense amplifiers formed on the semiconductor memory chip for each of said plurality of sub arrays and connected to said plurality of bit lines, each for sensing and amplifying a potential read out from a memory cell when a corresponding bit line is selected;
- a plurality of data lines formed on the semiconductor memory chip for said plurality of sub arrays and extending in the first direction in which said word lines extend, each of said plurality of data lines being connected to the sense amplifiers of a corresponding sub array, for transferring data sensed and amplified by a sense amplifier the bit line connected to which is selected;
- a plurality of multiplexer circuits formed on the semiconductor memory chip in the second direction and in parallel to the second edge of the semiconductor memory chip, each of said plurality of multiplexer circuits being connected to one of said sub arrays of each of said banks;
- a plurality of data buffer circuits formed on the semiconductor memory chip in the second direction and in parallel to the second edge of the semiconductor memory chip, each of said plurality of data buffer circuits being connected to a corresponding multiplexer circuit;
- and
- a plurality of input/output nodes connected to said data buffer circuits, said input/output nodes being in an arrangement in the second direction on the semiconductor memory chip and being in parallel to the second edge of the semiconductor memory chip, the arrangement being closer to the second edge of the semiconductor memory chip than said data buffer circuits and said multiplexer circuits.
7 more elements
A semiconductor memory device comprising:
- a semiconductor chip formed on a semiconductor substrate;
- a memory cell array formed on said semiconductor chip, said memory cell array comprising sub arrays organized into memory banks which are spaced apart from each other in one of a first and a second direction;
- multiplexer circuits formed on said semiconductor chip and spaced apart from each other in the second direction, each multiplexer circuit being connected to a sub array from each memory cell bank;
- data buffer circuits formed on said semiconductor chip and spaced apart from each other in the second direction, each data buffer circuit being connected to a corresponding multiplexer circuit;
- input/output nodes formed on said semiconductor chip and spaced apart from each other in the second direction, each input/output node being connected to a corresponding data buffer circuit;
- and
- wherein said data buffer circuits and said multiplexer circuits are arranged between said input/output nodes and said sub arrays.
4 more elements
A semiconductor memory device comprising:
- a semiconductor chip formed on a semiconductor substrate;
- a memory cell array formed on said semiconductor chip, said memory cell array comprising sub arrays organized into memory banks which are spaced apart from each other in one of a first and a second direction, each sub array comprising memory cells arranged in rows and columns;
- word lines extending in the first direction and provided for each sub array, each word line connecting memory cells in a row of the corresponding sub array;
- bit lines extending in the second direction and provided for each sub array, each bit line connecting memory cells in a column of the corresponding sub array;
- multiplexer circuits formed on said semiconductor chip and spaced apart from each other in the second direction;
- data buffer circuits formed on said semiconductor chip and spaced apart from each other in the second direction;
- data lines including at least data line portions extending in the first direction and connecting said sub arrays and said multiplexer circuits such that each multiplexer circuit is connected to a sub array from each memory cell bank;
- input/output nodes formed on said semiconductor chip and spaced apart from each other in the second direction, each input/output node being connected to a corresponding data buffer circuit;
- and
- wherein said data buffer circuits and said multiplexer circuits are arranged between said input/output nodes and said sub arrays.
7 more elements
A dynamic type memory comprising:
- a memory cell array formed on a semiconductor chip having a first edge and a second edge perpendicular to the first edge;
- a plurality of sub arrays into which said memory cell array is divided, said plurality of sub arrays being arranged in a first direction parallel to the first edge and a second direction perpendicular to said first direction, and grouped into a plurality of banks, each of said plurality of sub arrays having a plurality of memory cells arranged in matrix;
- a plurality of word lines formed on the semiconductor memory chip for each of said plurality of sub arrays and extending in the first direction, each of said plurality of word lines being connected to those of the memory cells which are in a row;
- a plurality of bit lines formed on the semiconductor memory chip for each of said plurality of sub arrays and extending in the second direction, each of said plurality of bit lines being connected to those of the memory cells which are in a column;
- a plurality of sense amplifiers formed on the semiconductor memory chip for each of said plurality of sub arrays and connected to said plurality of bit lines, each for sensing and amplifying a potential read out from a memory cell when a corresponding bit line is selected;
- a plurality of data lines formed on the semiconductor memory chip for said plurality of sub arrays and extending in the first direction in which said word lines extend, each of said plurality of data lines being connected to the sense amplifiers of a corresponding sub array, for transferring data sensed and amplified by a sense amplifier the bit line connected to which is selected;
- a plurality of switch circuits formed on the semiconductor memory chip in the second direction and in parallel to said second edge of said semiconductor memory chip, each of said plurality of switch circuits being connected to one of said sub arrays of each of said banks;
- a plurality of data buffer circuits formed on the semiconductor memory chip in the second direction and in parallel to said second edge of said semiconductor memory chip, each of said plurality of data buffer circuits being connected to a corresponding switch circuit;
- and
- a plurality of input/output nodes connected to said data buffer circuits, the input/output nodes being in an arrangement in the second direction on the semiconductor memory chip and being in parallel to said second edge of said semiconductor memory chip, the arrangement being closer to the second edge of the semiconductor memory chip than said data buffer circuits and said switch circuits.
7 more elements
A semiconductor memory device comprising:
- a semiconductor chip formed on a semiconductor substrate;
- a memory cell array formed on said semiconductor chip, said memory cell array comprising sub arrays organized into memory banks which are spaced apart from each other in one of a first and a second direction;
- switch circuits formed on said semiconductor chip and spaced apart from each other in the second direction, each switch circuit being connected to a sub array from each memory cell bank;
- data buffer circuits formed on said semiconductor chip and spaced apart from each other in the second direction, each data buffer circuit being connected to a corresponding switch circuit;
- input/output nodes formed on said semiconductor chip and spaced apart from each other in the second direction, each input/output node being connected to a corresponding data buffer circuit;
- and
- wherein said data buffer circuits and said switch circuits are arranged between said input/output nodes and said sub arrays.
4 more elements
A semiconductor memory device comprising:
- a semiconductor chip formed on a semiconductor substrate;
- a memory cell array formed on said semiconductor chip, said memory cell array comprising sub arrays organized into memory banks which are spaced apart from each other in one of a first and a second direction, each sub array comprising memory cells arranged in rows and columns;
- word lines extending in the first direction and provided for each sub array, each word line connecting memory cells in a row of the corresponding sub array;
- bit lines extending in the second direction and provided for each sub array, each bit line connecting memory cells in a column of the corresponding sub array;
- switch circuits formed on said semiconductor chip and spaced apart from each other in the second direction;
- data buffer circuits formed on said semiconductor chip and spaced apart from each other in the second direction;
- data lines including at least data line portions extending in the first direction and connecting said sub arrays and said switch circuits such that each switch circuit is connected to a sub array from each memory cell bank;
- input/output nodes formed on said semiconductor chip and spaced apart from each other in the second direction, each input/output node being connected to a corresponding data buffer circuit;
- and
- wherein said data buffer circuits and said switch circuits are arranged between said input/output nodes and said sub arrays.
7 more elements
A dynamic type memory comprising:
- a memory cell array formed on a semiconductor chip having a first edge and a second edge perpendicular to the first edge;
- a plurality of sub arrays into which said memory cell array is divided, said plurality of sub arrays being arranged in a first direction parallel to the first edge and a second direction perpendicular to said first direction, and grouped into a plurality of banks, each of said plurality of sub arrays having a plurality of memory cells arranged in matrix;
- a plurality of word lines formed on the semiconductor memory chip for each of said plurality of sub arrays and extending in the first direction, each of said plurality of word lines being connected to those of the memory cells which are in a row;
- a plurality of bit lines formed on the semiconductor memory chip for each of said plurality of sub arrays and extending in the second direction, each of said plurality of bit lines being connected to those of the memory cells which are in a column;
- a plurality of sense amplifiers formed on the semiconductor memory chip for each of said plurality of sub arrays and connected to said plurality of bit lines, each for sensing and amplifying a potential read out from a memory cell when a corresponding bit line is selected;
- a plurality of data lines formed on the semiconductor memory chip for said plurality of sub arrays and extending in the first direction in which said word lines extend, each of said plurality of data lines being connected to the sense amplifiers of a corresponding sub array, for transferring data sensed and amplified by a sense amplifier the bit line connected to which is selected;
- a plurality of multiplexer circuits formed on the semiconductor memory chip in the second direction and in parallel to said second edge of said semiconductor memory chip, each of said plurality of multiplexer circuits being connected to one of said sub arrays of each of said banks;
- and
- a plurality of data buffer circuits formed on the semiconductor memory chip in the second direction and in parallel to said second edge of said semiconductor memory chip, each of said plurality of data buffer circuits being connected to a corresponding multiplexer circuit.
6 more elements
A semiconductor memory device comprising:
- a semiconductor chip formed on a semiconductor substrate;
- a memory cell array formed on said semiconductor chip, said memory cell array comprising sub arrays organized into memory banks which are spaced apart from each other in one of a first and a second direction;
- multiplexer circuits formed on said semiconductor chip and spaced apart from each other in the second direction, each multiplexer circuit being connected to a sub array from each memory cell bank;
- data buffer circuits formed on said semiconductor chip and spaced apart from each other in the second direction, each data buffer circuit being connected to a corresponding multiplexer circuit;
- and
- wherein said multiplexer circuits are arranged between said data buffer circuits and said sub arrays.
3 more elements
A semiconductor memory device comprising:
- a semiconductor chip formed on a semiconductor substrate;
- a memory cell array formed on said semiconductor chip, said memory cell array comprising sub arrays organized into memory banks which are spaced apart from each other in one of a first and a second direction, each sub array comprising memory cells arranged in rows and columns;
- word lines extending in the first direction and provided for each sub array, each word line connecting memory cells in a row of the corresponding sub array;
- bit lines extending in the second direction and provided for each sub array, each bit line connecting memory cells in a column of the corresponding sub array;
- multiplexer circuits formed on said semiconductor chip and spaced apart from each other in the second direction;
- data buffer circuits formed on said semiconductor chip and spaced apart from each other in the second direction;
- data lines including at least data line portions extending in the first direction and connecting said sub arrays and said multiplexer circuits such that each multiplexer circuit is connected to a sub array from each memory cell bank;
- and
- wherein said multiplexer circuits are arranged between said data buffer circuits and said sub arrays.
6 more elements
A dynamic type memory comprising:
- a memory cell array formed on a semiconductor chip having a first edge and a second edge perpendicular to the first edge;
- a plurality of sub arrays into which said memory cell array is divided, said plurality of sub arrays being arranged in a first direction parallel to the first edge and a second direction perpendicular to said first direction, and grouped into a plurality of banks, each of said plurality of sub arrays having a plurality of memory cells arranged in matrix;
- a plurality of word lines formed on the semiconductor memory chip for each of said plurality of sub arrays and extending in the first direction, each of said plurality of word lines being connected to those of the memory cells which are in a row;
- a plurality of bit lines formed on the semiconductor memory chip for each of said plurality of sub arrays and extending in the second direction, each of said plurality of bit lines being connected to those of the memory cells which are in a column;
- a plurality of sense amplifiers formed on the semiconductor memory chip for each of said plurality of sub arrays and connected to said plurality of bit lines, each for sensing and amplifying a potential read out from a memory cell when a corresponding bit line is selected;
- a plurality of data lines formed on the semiconductor memory chip for said plurality of sub arrays and extending in the first direction in which said word lines extend, each of said plurality of data lines being connected to the sense amplifiers of a corresponding sub array, for transferring data sensed and amplified by a sense amplifier the bit line connected to which is selected;
- a plurality of switch circuits formed on the semiconductor memory chip in the second direction and in parallel to said second edge of said semiconductor memory chip, each of said plurality of switch circuits being connected to one of said sub arrays of each of said banks;
- and
- a plurality of data buffer circuits formed on the semiconductor memory chip in the second direction and in parallel to said second edge of said semiconductor memory chip, each of said plurality of data buffer circuits being connected to a corresponding switch circuit.
6 more elements
A semiconductor memory device comprising:
- a semiconductor chip formed on a semiconductor substrate;
- memory cell array formed on said semiconductor chip, said memory cell array comprising sub arrays organized into memory banks which are spaced apart from each other in one of a first and a second direction;
- switch circuits formed on said semiconductor chip and spaced apart from each other in the second direction, each switch circuit being connected to a sub array from each memory cell bank;
- data buffer circuits formed on said semiconductor chip and spaced apart from each other in the second direction, each data buffer circuit being connected to a corresponding switch circuit;
- and
- wherein said switch circuits are arranged between said data buffer circuits and said sub arrays.
3 more elements
A semiconductor memory device comprising:
- a semiconductor chip formed on a semiconductor substrate;
- a memory cell array formed on said semiconductor chip, said memory cell array comprising sub arrays organized into memory banks which are spaced apart from each other in one of a first and a second direction, each sub array comprising memory cells arranged in rows and columns;
- word lines extending in the first direction and provided for each sub array, each word line connecting memory cells in a row of the corresponding sub array;
- bit lines extending in the second direction and provided for each sub array, each bit line connecting memory cells in a column of the corresponding sub array;
- switch circuits formed on said semiconductor chip and spaced apart from each other in the second direction;
- data buffer circuits formed on said semiconductor chip and spaced apart from each other in the second direction;
- data lines including at least data line portions extending in the first direction and connecting said sub arrays and said switch circuits such that each switch circuit is connected to a sub array from each memory cell bank;
- and
- wherein said switch circuits are arranged between said data buffer circuits and said sub arrays.
6 more elements
Dependencies are inferred from the claim text.