Mixed technology integrated device comprising complementary LDMOS power transistors, CMOS and vertical PNP integrated structures having an enhanced ability to withstand a relatively high supply voltage

An integrated circuit fabricated in a silicon layer having a first conductivity type on a substrate having a second conductivity type opposite that of the first conductivity type, the integrated circuit including first and second LDMOS transistors, a MOS transistor, and an isolated collector vertical bipolar transistor, comprising:

• a drain region of the first LDMOS transistor having the first conductivity type and extending from a surface of the silicon layer to a sufficient depth to contain a shallower more heavily doped region of the first conductivity type formed in the drain region;
• a body region of the second LDMOS transistor formed in a region of the silicon layer doped to have the second conductivity type, the body region having the first conductivity type and extending from the surface of the silicon layer to a sufficient depth to contain a shallower more heavily doped region of the second conductivity type formed in the body region;
• a drain region of the MOS transistor formed in a region of the silicon layer doped to have the second conductivity type, the drain region having the first conductivity type and extending from the surface of the silicon layer to a sufficient depth to contain a shallower more heavily doped region of the first conductivity type formed in the drain region;
• and
• a base region of the isolated collector vertical bipolar transistor, the base region including a first region of the first conductivity type extending from the surface of the silicon layer to a depth greater than a depth of a shallower more heavily doped region of the second conductivity type formed in the first region, and the base region further including a second region in which the first region is formed, the second region formed from a portion of the silicon layer that is encompassed by a well region of the second conductivity type, the second region extending from the surface of the silicon layer to a depth greater than the depth of the first region.

An integrated circuit fabricated in a silicon layer having a first conductivity type on a substrate having a second conductivity type opposite that of the first conductivity type, comprising;

• a first LDMOS transistor having a drain region between a gate electrode of the first LDMOS transistor and an adjacent isolation field oxide, the drain region having the first conductivity type and extending from a surface of the silicon layer to a sufficient depth to contain a shallower more heavily doped region of the first conductivity type;
• a second LDMOS transistor having a body region between a gate electrode of the second LDMOS transistor and an adjacent isolation field oxide, the body region having the first conductivity type and extending from the surface of the silicon layer to a sufficient depth to contain a shallower more heavily doped region of the second conductivity type;
• a MOS transistor having a drain region between a gate electrode of the MOS transistor and an adjacent isolation field oxide, the drain region having the first conductivity type and extending from the surface of the silicon layer to a sufficient depth to contain a shallower more heavily doped region of the first conductivity type;
• and
• an isolated collector vertical bipolar transistor having a base region surrounded by an isolation field oxide, the base region having a first region of the first conductivity type that extends from the surface of the silicon layer to a sufficient depth to contain a shallower more heavily doped region of the second conductivity type and the base region further having a second region formed from a portion of the silicon layer that is encompassed by a well region of the second conductivity type, the second region extending from the surface of the silicon layer to a sufficient depth to contain the first region.

An integrated circuit, comprising:

• a p-type substrate;
• an n-type epitaxial silicon layer overlying the p-type substrate, the n-type epitaxial silicon layer having a surface;
• an n-channel LDMOS transistor having a drain region between a gate electrode of the n-channel LDMOS transistor and an adjacent isolation field oxide, the drain region having an n− type doping profile extending from the surface of the n-type epitaxial silicon layer to a sufficient depth to contain a shallower more heavily doped region which has an n+ type doping profile;
• a p-channel LDMOS transistor having a body region between a gate electrode of the p-channel LDMOS transistor and an adjacent isolation field oxide, the body region having an n− type doping profile extending from the surface of the n-type epitaxial silicon layer to a sufficient depth to contain a shallower more heavily doped region which has a p+ type doping profile;
• an n-channel MOS transistor having a drain region between a gate electrode of the n-channel MOS transistor and an adjacent isolation field oxide, the drain region having an n− type doping profile extending from the surface of the n-type epitaxial silicon layer to a sufficient depth to contain a shallower more heavily doped region which has an n+ type doping profile;
• a p-channel MOS transistor;
• and
• an isolated collector, vertical PNP transistor having a base region surrounded by an isolation field oxide, the base region having a first region with an n− type doping profile that extends from the surface of the n-type epitaxial silicon layer to a sufficient depth to contain a shallower more heavily doped p+ emitter region, and the base region further having a second region formed from a portion of the n-type epitaxial silicon layer that is encompassed by a p-well region, the second region extending from the surface of the n-type epitaxial silicon layer to a sufficient depth to contain the first region.

An integrated circuit, comprising:

• a p-type substrate;
• an n-type epitaxial silicon layer overlying the p-type substrate, the n-type epitaxial silicon layer having a surface;
• an n-channel LDMOS transistor, including
• a drain region formed in the n-type epitaxial layer between a gate electrode of the n-channel LDMOS transistor and an adjacent isolation field oxide, the drain region having a diffused n− doping profile extending from the surface of the n-type epitaxial silicon layer to a sufficient depth to contain a shallower more heavily doped region that has an n+ type doping profile, and
• a body region formed in the n-type epitaxial layer between the gate electrode of the n-channel LDMOS transistor and an adjacent isolation field oxide, the body region having a p-type doping profile extending from the surface of the n-type epitaxial silicon layer to a sufficient depth to contain a shallower more heavily doped n+ type source region;
• a p-channel LDMOS transistor, including
• a drain region between a gate electrode of the p-channel LDMOS transistor and an adjacent isolation field oxide, the drain region having a p-type doping profile extending from the surface of the n-type epitaxial silicon layer to a sufficient depth to contain a shallower more heavily doped region which has a p+ type doping profile, and
• a body region between the gate electrode of the p-channel LDMOS transistor and an adjacent isolation field oxide, the body region having a diffused n− doping profile extending from the surface of the n-type epitaxial silicon layer to a sufficient depth to contain a shallower more heavily doped p+ type source region;
• an n-channel MOS transistor, including
• a drain region between a gate electrode of the n-channel MOS transistor and an adjacent isolation field oxide, the drain region having a diffused n− doping profile extending from the surface of the n-type epitaxial silicon layer to a sufficient depth to contain a shallower more heavily doped region that has an n+ type doping profile, and
• an n+ type source region formed in a p-well region between the gate electrode of the n-channel MOS transistor and an adjacent isolation field oxide;
• a p-channel MOS transistor, including
• a p+ type drain region formed in the n-type epitaxial layer between a gate electrode of the p-channel MOS transistor and an adjacent isolation field oxide, and
• a p+ type source region formed in the n-type epitaxial layer between the gate electrode of the p-channel MOS transistor and an adjacent isolation field oxide;
• and
• an isolated collector vertical PNP transistor, including
• a base region surrounded by an isolation field oxide and including a first region with a diffused n− doping profile that extends from the surface of the n-type epitaxial silicon layer to a sufficient depth to contain a shallower more heavily doped p+ emitter region, the base region further having a second region comprising a portion of the n-type epitaxial silicon layer that is encompassed in a p-well region, the second region extending from the surface of the n-type epitaxial silicon layer to a sufficient depth to contain the first region, and an n+ type region formed between an isolation field oxide and the isolation field oxide surrounding the base region to extend from the surface of the n-type epitaxial silicon layer into the second region;
• and
• an isolated collector region extending into the p-well encompassing the second region.

An integrated circuit fabricated in an n-type silicon layer on a p-type substrate, comprising:

• an n-channel LDMOS transistor including an n+ source region contact having a depth and a p-type body region in the silicon layer surrounding and having a depth greater than the depth of the n+ source region contact, a gate capacitively coupled to the p-type body region near the source region contact to create a voltage-controlled conduction channel in the body region, and an n+ drain region contact having a depth and a diffused n− lightly-doped drain region in the silicon layer surrounding and having a depth greater than the depth of the n+ drain region contact, the n+ drain region contact positioned on the opposite side of the channel as the n+ source region contact;
• and
• a p-channel LDMOS transistor including a p+ source region contact having a depth and a diffused n− lightly-doped body region in a p-doped portion of the n-type silicon layer surrounding and having a depth greater than the depth of the p+ source region contact, a gate capacitively coupled to the body region near the source region contact to create a voltage-controlled conduction channel in the body region, and a p+ drain region contact having a depth and a p-type lightly-doped drain region in the p-doped portion of the silicon layer surrounding and having a depth greater than the depth of the p+ drain region contact, the p+ drain region contact positioned on the opposite side of the channel as the p+ source region contact.

A method for fabricating an integrated circuit, comprising the steps of:

• providing a semiconductor substrate having a first conductivity type;
• forming on the substrate a silicon layer having a second conductivity type;
• forming in the silicon layer a first region of the second conductivity type, a second region of the first conductivity type adjacent the first region, a third region of the first conductivity type isolated by an isolation region from the second region, and forming a fourth region of the second conductivity type in a portion of first-conductivity type formed in the silicon layer;
• diffusing simultaneously into each of the first, second, third and fourth regions an impurity of the second conductivity type to form in each of the respective regions a diffused region, each diffused region having the same dopant concentration and depth;
• and
• diffusing into the diffused regions an additional dopant of a higher concentration to a depth more shallow than the depth of the diffused regions to form a more highly doped region in each of the diffused regions.