Synchronous LSI memory device

A synchronous LSI memory device supplied with a clock signal, a stop signal and a control signal, comprising:

• memory cell array means each having a plurality of memory cells;
• timing generating means for generating a first basic signal synchronous with the clock signal and masked according to status of the control signal;
• signal generating means for generating a second signal in synchronism with the first basic signal and stopping generating the second signal after a predetermined number of accesses of the memory cells or in response to the stop signal;
• control means for controlling said memory cell array means on the basis of outputs of said timing generating means and said signal generating means;
• mask control means for acquiring statuses of terminals in sequence into register means having a number of bits that are an even-number times larger than that obtained during a cycle interval during which a column address is inputted, outputting the acquired data in sequence, inputting the outputted data, respectively, to specific registers each having the number of bits that are an even-number times larger than that obtained during the cycle interval during which the column address is inputted, and when data inputted through the terminals are in a first status, outputting signals for setting output circuits of the register means to a high impedance status in synchronism with the second signal;
• read mask registers for acquiring, in a read mode, the statuses of the second terminals into a plurality of registers in sequence in synchronism with the second signal, and outputting the acquired data to data lines in sequence;
• and
• potential fixing means for fixing, in a write mode, potentials of the data lines to set output circuits connected to the data lines to a high impedance status.

A synchronous LSI memory device supplied with a clock signal, a stop signal, and a control signal, comprising:

• memory cell array means each having a plurality of memory cells;
• timing generating means for generating a first basic signal synchronous with the clock signal and masked according to status of the control signal;
• signal generating means for generating a second signal in synchronism with the first basic signal and stopping generating the second signal after a predetermined number of accesses of the memory cells or in response to the stop signal;
• and
• control means for controlling said memory cell array means on the basis of outputs of said timing generating means and said signal generating means,
• wherein the stop signal is outputted subsequent to a predetermined number of accesses of the memory cells after the memory cells have been precharged by a precharge means.

A synchronous LSI memory device supplied with a clock signal, a stop signal, and a control signal, comprising:

• memory cell array means each having a plurality of memory cells;
• timing generating means for generating a first basic signal synchronous with the clock signal and masked according to status of the control signal;
• signal generating means for generating a second signal in synchronism with the first basic signal and stopping generating the second signal after a predetermined number of accesses of the memory cells or in response to the stop signal;
• and
• control means for controlling said memory cell array means on the basis of outputs of said timing generating means and said signal generating means, wherein the number of predetermined accesses is counted on the basis of a signal for selecting bits n-bits by n-bits by interleaving an m(=n+n)-bit register having two sets of n-bit registers.

A synchronous LSI memory device supplied with a clock signal, a stop signal, and a control signal, comprising:

• memory cell array means each having a plurality of memory cells;
• timing generating means for generating a first basic signal synchronous with the clock signal and masked according to status of the control signal;
• signal generating means for generating a second signal in synchronism with the first basic signal and stopping generating the second signal after a predetermined number of accesses of the memory cells or in response to the stop signal;
• and
• control means for controlling said memory cell array means on the basis of outputs of said timing generating means and said signal generating means,
• wherein when a plurality of said memory cells are accessed in series, a plurality of serially accessed memory cells can be accessed simultaneously.

A synchronous LSI memory device supplied with a clock signal, a stop signal, and a control signal, comprising:

• memory cell array means each having a plurality of memory cells;
• timing generating means for generating a first basic signal synchronous with the clock signal and masked according to status of the control signal;
• signal generating means for generating a second signal in synchronism with the first basic signal and stopping generating the second signal after a predetermined number of accesses of the memory cells or in response to the stop signal;
• and
• control means for controlling said memory cell array means on the basis of outputs of said timing generating means and said signal generating means,
• wherein the second signal is divided into a plurality of signals according to use so as to be controlled individually.

A synchronous memory device operable in response to a clock signal, bank select address signals, address signals, /CS (inverted Chip Select Signal), /RAS (inverted Row Address Strobe signal), /CAS (inverted Column Address Strobe signal) and /WE (inverted Write Enable signal), and outputting data to DQ (Data Input/Output) terminal, comprising:

• a memory cell array divided into a plurality of banks, each of the banks being precharged and being activated in response to the bank select address signals, each of the banks having a plurality of memory cells arranged in a matrix form, and each of the memory cells being selected in response to address signals;
• a mode register configured to store an operand code;
• and
• a control circuit operable in response to the clock signal, the bank select address signals, the address signals, the inverted Chip Select signal, the inverted Row Address Strobe signal, the inverted Column Address Strobe signal, and the inverted Write Enable signal, the control circuit configured to render the bank select address signals and the address signals to be valid and to set the operand code to the mode register when the inverted Chip Select signal is in a low level, the inverted Row Address Strobe signal is in the low level, the inverted Column Address Strobe signal is in the low level, and the inverted Write Enable signal is in the low level and when the clock signal changes,
• wherein the operand code is issued when all of the banks of the memory cell array are precharged.