Parallel type nonvolatile semiconductor memory device and method of using the same

In combination with a semiconductor memory device comprising memory arrays connected in parallel,

• wherein each memory array has a plurality of memory cells which are electrically erasable and programmable, comprising MOS field effect transistors each having a control gate, a floating gate, a gate insulation film, a drain region and a source region formed on a semiconductor substrate, which are arranged in a matrix including plural rows and columns of memory cells over a surface of said semiconductor substrate,
• the control gates of memory cells in a single row are connected to each other by a word line corresponding to that row,
• the drain regions of memory cells in a single column are connected to each other by a data line corresponding to that column, and
• the source regions of memory cells in a single column are connected to each other by a source line corresponding to that column,
• the improvement which comprises a parallel type nonvolatile semiconductor memory device characterized in that:
• each of said memory cells is comprised of one of said MOS field effect transistors, the MOS field effect transistors of memory cells disposed in each column having both the drain region and the source region thereof formed within a well layer, common to that column, formed on said semiconductor substrate which is of a first conductivity type, said well layer having the same conductivity type as that of said semiconductor substrate and being electrically separated from said semiconductor substrate,
• well layers of memory cells associated with different columns are commonly connected through well wiring,
• each said source line has a switching element connected thereto, said switching element comprising a MOS transistor having a drain region and source region thereof formed within the well layer of that column, and each said source line being connected through said switching element connected thereto to a common source line,
• said memory cells are divided into a plurality of blocks each of which has, in each column associated therewith, memory cells which are connected thereto, a respective said source line and a respective said switching element and has a rate wiring by which rates of switching elements in the corresponding block are connected to each other,
• all switching elements of a block are driven by the gate wiring thereof and are held to an off-state during the data erasing period and during the data programming period of that block, and
• each of said memory cells has a channel region under the floating gate the entirety of which is used to generate the Fowler-Nordheim tunnel phenomena.