Programmable switch for FPGA input/output signals

A programmable logic device comprising:

• a set of pads for receiving signals from a source external to the programmable logic device or providing signals to a destination external to the programmable logic device;
• a user logic portion for receiving input signals from said pads and providing one or more output signals to one or more of said pads;
• a configurable memory for configuring said user logic portion;
• and
• a switch for coupling at least one output signal from said user logic portion to said configuration memory so that said output signal can be stored in said configuration memory.

A programmable logic device comprising:

• a set of pads for receiving signals from a source external to the programmable logic device or providing signals to a destination external to the programmable logic device;
• a user logic portion for receiving input signals from and providing one or more output signals to said pads;
• a configuration memory for configuring said user logic portion;
• circuitry for receiving control signals and data signals and storing said data signals in said configuration memory in response to said control signals;
• and
• a switch for receiving an output signal from said user logic portion and applying said output signal as a control signal to said circuitry for receiving.

A programmable logic device comprising:

• a set of pads for receiving signals from a source external to the programmable logic device or providing signals to a destination external to the programmable logic device;
• a user logic portion for receiving input signals from and providing one or more output signals to said pads;
• a configuration memory for configuring said user logic portion;
• circuitry for receiving control signals and providing data signals from said configuration memory in response to said control signals;
• and
• a switch for receiving an output signal from said user logic portion and applying said output signal as a control signal to said circuitry for receiving.

A programmable logic device comprising:

• a set of pads for receiving signals from a source external to the programmable logic device or providing signals to a destination external to the programmable logic device;
• a user logic portion for receiving input signals from said pads and for providing one or more output signals on said pads;
• a configuration memory for configuring said user logic portion;
• a switch for receiving a first output signal from said configuration memory and a second output signal from said user logic portion and providing said first or second output signals to one of said pads, said switch being controlled by a third output signal from said user logic portion.

A programmable logic device comprising:

• a user logic portion for performing selected logic functions;
• a configuration memory for controlling the functions performed by said user logic portion;
• a set of pads for receiving signals from an external source, at least some of said signals comprising data signals to be stored in said configuration memory;
• and
• circuitry for selecting locations within said configuration memory for receiving said data signals, said locations being selected in part by said user logic portion.

A programmable logic device comprising:

• a set of pads for receiving signals from a source external to the programmable logic device or providing signals to a destination external to the programmable logic device;
• a user logic portion for receiving input signals from said pads and providing one or more output signals to one or more of said pads;
• a configurable memory for configuring said user logic portion;
• and
• means for coupling at least one output signal from said user logic portion to said configuration memory so that said output signal can be stored in said configuration memory.

A programmable logic device comprising:

• a set of pads for receiving signals from a source external to the programmable logic device or providing signals to a destination external to the programmable logic device;
• a user logic portion for receiving input signals from and providing one or more output signals to said pads;
• a configuration memory for configuring said user logic portion;
• circuitry for receiving control signals and data signals and storing said data signals in said configuration memory in response to said control signals;
• and
• means for receiving an output signal from said user logic portion and applying said output signal as a control signal to said circuitry for receiving.

A programmable logic device comprising:

• a set of pads for receiving signals from a source external to the programmable logic device or providing signals to a destination external to the programmable logic device;
• a user logic portion for receiving input signals from and providing one or more output signals to said pads;
• a configuration memory for configuring said user logic portion;
• circuitry for receiving control signals and providing data signals from said configuration memory in response to said control signals;
• and
• means for receiving an output signal from said user logic portion and applying said output signal as a control signal to said circuitry for receiving.

A programmable logic device comprising:

• a set of pads for receiving signals from a source external to the programmable logic device or providing signals to a destination external to the programmable logic device;
• a user logic portion for receiving input signals from said pads and for providing one or more output signals on said pads;
• a configuration memory for configuring said user logic portion;
• means for receiving a first output signal from said configuration memory and a second output signal from said user logic portion and providing said first or second output signals to one of said pads, said means for receiving being controlled by a third output signal from said user logic portion.

A programmable logic device comprising:

• a user logic portion for performing selected logic functions;
• a configuration memory for controlling the functions performed by said user logic portion;
• a set of pads for receiving signals from an external source, at least some of said signals comprising data signals to be stored in said configuration memory;
• and
• means for selecting locations within said configuration memory for receiving said data signals, said locations being selected in part by said user logic portion.

A programmable logic device comprising:

• a user logic structure;
• a configuration memory for controlling said user logic structure;
• a structure for accessing said configuration memory;
• a plurality of pads for connecting external signals to said programmable logic device;
• means for connecting signals between said pads, said user logic structure, and said structure for accessing said configuration memory, said means for connecting being controlled by said configuration memory.

In a programmable logic device comprising:

• a) a user logic section having user memory devices;
• b) a configuration memory comprising a set of memory cells for storing configuration data and for controlling the function performed by the user logic;
• and
• c) a configuration memory interface circuit for loading data into or reading data out of said configuration memory,
• a method for swapping data in and out of a configurable logic device comprising:
• a) using said configuration memory interface for reading data stored in said user memory devices;
• and
• b) using said configuration memory interface for writing new data into said user memory devices.

A programmable logic device comprising:

• a programmable user logic portion for performing selected logic functions, said programmable logic user portion comprising a set of user memory cells for storing user logic signals;
• a configuration memory section comprising a set of configuration memory cells, the data stored in said configuration memory section controlling the logic function performed by said user logic portion;
• and
• a configuration memory interface for writing data to said configuration memory cells, said configuration memory interface also being coupled to said user memory cells said configuration memory interface being used to read data from said user memory cells and to write data to said user memory cells.

Programmable logic device comprising:

• a programmable user logic portion for performing selected logic functions, said user logic portion comprising user memory cells for storing user logic signals;
• a configuration memory for controlling the function performed by said programmable user logic portion;
• a set of input/output pads;
• configuration memory interface means for receiving data from said input/output pads and storing data in said configuration memory, said configuration memory interface means also storing data in and reading data from said user memory cells.

In a circuit comprising a) at least one bit line;

• b) a set of memory cells;
• and c) a set of switches for coupling said memory cells to said bit line, a method for setting said memory cells to a logic value comprising:
• applying a signal on said bit line, said signal corresponding to said logic value;
• coupling a first subset of said memory cells to said bit line, whereby said first subset of memory cells are set to said logic value;
• and
• thereafter coupling a second subset of memory cells to said bit line while said first subset of memory cells are coupled to said bit line, whereby said second subset of memory cells are set to said logic value.

Structure comprising:

• a bit line;
• a driver for applying a value to said bit line;
• a set of memory cells;
• a set of switches for coupling said set of memory cells to said bit line, said driver setting said memory cells to an initial value, wherein when said driver sets said memory cells to said initial value, a first subset of switches within said set of switches closes to couple a first subset of memory cells within said set of memory cells to said bit line to set said first subset of memory cells to said initial value, and thereafter a second subset of switches within said set of switches closes to couple a second subset of memory cells within said set of memory cells to said bit lines to set said second subset of memory cells to said initial value.

Structure comprising:

• a bit line;
• a driver for applying a value to said bit line;
• a set of memory cells;
• switch means for coupling said set of memory cells to said bit line, said driver setting said memory cells to an initial value, wherein when said driver sets said memory cells to said initial value, said switch means couples a first subset of memory cells within said set of memory cells to said bit line to set said first subset of memory cells to said initial value, and thereafter said switch means couples a second subset of memory cells within said set of memory cells to said bit lines to set said second subset of memory cells to said initial value.

In a programmable logic device having configuration memory, logic, and pads, a switch programmable to connect:

• a selected one of the pads to the configuration memory;
• a selected one of the pads to a selected terminal of the logic;
• and
• a selected terminal of the logic to the configuration memory.