Planarization of a gate electrode for improved gate patterning over non-planar active area isolation
AssigneeMicron Technology, Inc.
InventorsTrung T. Doan, Charles H. Dennison
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Abstract
The present invention is a process for providing a planarized transistor gate on a non-planar starting substrate, by depositing a layer of planarized conductive polysilicon material overlying neighboring field oxide isolation regions such that the height of the conductive polysilicon material extends above the topology topography of the field oxide isolation regions; depositing a layer of conductive silicide material superjacent and coextensive the conductive polysilicon material; and then patterning the planarized conductive polysilicon material and the conductive silicide material thereby forming the planarized transistor gate.
Claims61
A process for providing a planarized conductor on a non-planar starting substrate, said process comprising the steps of:
- forming a layer of planarized conductive material overlying neighboring isolation regions such that the height of said planarized conductive material layer extends above the topology topography of said neighboring isolation regions;
- forming a layer of reflective material superjacent and coextensive said planarized conductive material layer;
- and
- patterning said planarized conductive material layer thereby forming said planarized conductor.
A process for providing a planarized transistor gate on a non-planar starting substrate, said process comprising the steps of:
- forming a layer of planarized conductive material overlying neighboring isolation regions such that the height of said planarized conductive material layer extends above the topology topography of said neighboring isolation regions;
- forming a layer of reflective material superjacent and coextensive said planarized conductive material layer;
- and
- patterning said planarized conductive material layer thereby forming said thereby forming said planarized transistor gate.
A process for providing a conductor on a non-planar substrate comprising:
- forming a layer of conductive material on said non-planar substrate such that the height of said layer of conductive material extends above the topography of said non-planar substrate;
- planarizing said conductive material layer;
- forming a layer of at least partially reflective material over said planarized conductive material layer;
- and
- patterning said planarized conductive material layer.
A process for providing a transistor gate on a non-planar substrate, said process comprising the steps of:
- forming a layer of conductive material on said non-planar substrate such that the height of said layer of conductive material extends above the topography of said non-planar substrate;
- planarizing said conductive material layer;
- forming a layer of at least partially reflective material over said planarized conductive material layer;
- and
- patterning said planarized conductive material layer.
A process for providing a conductor on a non-planar substrate comprising:
- forming a substantially planar layer of conductive material on said non-planar substrate such that the height of said substantially planar layer of conductive material extends above the topography of said non-planar substrate;
- forming a layer of at least partially reflective material over said substantially planar conductive material layer;
- and
- patterning said substantially planar conductive material layer.
A process for providing a transistor gate on a non-planar substrate, said process comprising the steps of:
- forming a substantially planar layer of conductive material on said non-planar substrate such that the height of said substantially planar layer of conductive material extends above the topography of said non-planar substrate;
- forming a layer of at least partially reflective material over said substantially planar conductive material layer;
- and
- patterning said substantially planar conductive material layer.
Dependencies are inferred from the claim text.