Apparatus for serial reading and writing of random access memory arrays

A programmable logic device comprising a plurality of configurable logic circuits, serially programmable random access memory, and interconnect resource connecting said configurable logic circuits and said serially programmable random access memory, said serially programmable random access memory comprising:

• at least one random access memory array including:
• a plurality of random access memory bits,
• a plurality of data input lines for entering data to be stored in said random access memory array,
• a plurality of address input lines and an address decoder for entering address information indicating in a write mode in which of said plurality of random access memory bits said data to be stored are to be stored, and for indicating in a read mode which of said plurality of random access memory bits are to be output from said random access memory, and
• a read/write control input, said random access memory array being in a read mode when a read/write control signal applied to said read/write control input is in a first logic state and being in a write mode when said read/write control signal applied to said read/write control input is in a second logic state;
• for each said at least one random access memory array, a set of input/programming registers connected to said data input lines, said address input lines and said read/write control input for inputting programming data for said random access memory array, said programming data including said address information and a registered control signal to be applied to said read/write control input, and including said data to be written when said input/programming registers are used for writing, said input/programming registers being chained together such that said programming data can be entered serially into said registers;
• and
• a read/write control circuit for selectively operating said at least one random access memory array in one of (a) a first mode in which said random access memory array is in one of (i) a read mode, and (ii) a write mode, regardless of said registered control signal, and (b) a second mode in which said random access memory array is in one of (i) a read mode, and (ii) a write mode, under control of said registered control signal.

An apparatus comprising:

• a memory array including a plurality of storage locations;
• and
• a serial register, coupled to said memory array, said serial register including:
• a first field configured to store an address corresponding to one of said plurality of memory locations in said memory array;
• a second field configured to store control information used to control access to said memory array, said control information indicating a write operation when said control information is in a first state and a read operation when said control information is in a second state;
• and
• a third field configured to store data to be written into said one of said plurality of memory locations corresponding to said address stored in said first field when said control information is in said first state.

An apparatus comprising:

• a memory array including a plurality of memory locations;
• and
• a serial register coupled to said memory array, said serial register including:
• a first field configured to store an address corresponding to one of said plurality of memory locations in said memory array;
• and
• a second field configured to store control information used to control access to said one of said plurality of memory locations in said memory array corresponding to said address in said first field of said serial register.