SIMD system having logic units arranged in stages of tree structure and operation of stages controlled through respective control registers

A parallel computer system using a single instruction stream multiple data stream (SIMD) method, including processor elements and a controller generating control and synchronization signals, said parallel computer system comprising:

• data collection means, connected between the processor elements and the controller and arranged in a [binary] tree structure having stages, for receiving output data from the processor elements responsive to the synchronization signal received by the processor elements from the controller, for performing a predetermined calculation responsive to the control signal based on the stages in the [binary] tree structure, and for outputting calculated data to the controller;
• and
• calculation control means, connected between said data collection means and the controller and arranged in series corresponding to each of the stages, for transmitting the control signal received from the controller to said data collection means based upon a pipe-line process,
• wherein said data collection means comprises a plurality of gathering logic units connected to each other in the [binary] tree structure having the stages, first gathering logic units of a first stage of the stages receives the output data from each of the processor elements and outputs first calculation data, second gathering logic units of a second stage of the stages receives the first calculation data obtained from the first stage, and the first calculation data obtained from the second stage is output to a final gathering logic unit of a final stage of the stages as second calculation data, and final calculation data obtained from the final gathering logic unit of the final stage responsive to said second calculation data is output to the controller, and
• wherein said calculation control means comprises a plurality of control registers each corresponding to one of the stages, each of the plurality of control registers connected in series to each other by the pipe-line method, and each of the plurality of control register sequentially outputting the control signal to each of the gather logic units in the corresponding stage.

A method of calculation processing, comprising:

• processing input data in parallel in plural processing units to produce parallel output data;
• combining the parallel output data using a tree combination of tree stages to produce calculated output data;
• and
• controlling said processing and controlling said tree stage combining at each stage to produce a predetermined calculated output data result.

An apparatus, comprising:

• parallel processing units processing input data in parallel to produce parallel output data;
• data combination units connected to said parallel processing units and combining the parallel output data using a tree combination having combining control at each stage to produce calculated output data;
• and
• a controller connected to said data combination units and said parallel processing units and controlling said processing and said combining to produce a predetermined calculated output data result.