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US RE36,024 EGranted
Electrostatic discharge protection circuit for semiconductor device
AssigneeMicron Technology, Inc.
InventorsFan Ho, Mitchel A. Daher
Life of this patent
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AssigneeMicron Technology, Inc.
InventorsFan Ho, Mitchel A. Daher
Estimating the term…
An ESD protection circuit (38) for a MOS device uses at least one electrically floating-base N+P-N+ transistor (43) connected between a metal bonding pad (40) and ground. The electrically floating base region (44) of each transistor is formed by a thin oxide region deposited over a substrate (50) of the MOS device. Because its N+ regions (42, 45) are made symmetrical about the floating base, each transistor conducts ESD pulses of both polarities equally. The beta of each transistor is made sufficiently large to withstand short-duration ESD current spikes. Current density is minimized by diffusing a deep N- well (54, 56) into each N+ region of each transistor to provide a larger effective conducting area. Low capacitance and higher breakdown voltage are achieved by eliminating the gate structure of prior art FET-based protection circuits.
An ESD protection structure for a MOS device having a bonding pad and a ..P-.!. substrate, comprising:
The structure of claim 1 in which the electrically floating ..elongated.!. base region comprises a depletion region located in the substrate and under a field oxide grown on the substrate. ..4. The structure of claim 1 in which the base region width is less than about one micron..!...5. The structure of claim 1 in which the first and second N+ regions each have a width greater than about four microns..!...6. The structure of claim 1 in which the depth of the first and second N- wells
An ESD protection structure for a MOS device having a bonding pad and a substrate, comprising:
The structure of claim 20 in which the ground line is electrically connected to any one of a reference ground, the substrate, a power supply voltage, and an ESD drain potential.
The structure of claim 20 in which the depletion region is located in the substrate under a field oxide grown on the substrate.
The structure of claim 20 in which the base region width is 0.7 microns.
The structure of claim 20 in which the depth of the first and second wells is 3.7 microns.
The structure of claim 20 in which the first semiconductor region functions as a collector and the second semiconductor region functions as an emitter.
The structure of claim 20 in which the first and second wells each form trenches in the substrate, and in which the electrical connections to each of the wells are formed by a linearly distributed set of contacts deposited on an elongated surface of each of the wells.
The structure of claim 20 in which the ESD pulses conform to one of a human model and a machine model of an electrical discharge pulse.
Dependencies are inferred from the claim text.