Predictive capacitance layout method for integrated circuits

A method for designing an integrated circuit layout, including simulating an integrated circuit on a computer, comprising the steps of:

• statistically determining a predictive interconnect capacitance for different types of integrated circuit layout nets;
• on the computer, calculating an average capacitance per unit wire length for the integrated circuit layout;
• on the computer, converting the predictive interconnect capacitance for each different type of net into a maximum wire length value using the calculated average capacitance;
• placing at least one net at a desired location in an integrated circuit layout design on the simulated integrated circuit, and estimating wire length of each net on the basis of the placement;
• on the computer, comparing the estimated wire length of each net with the maximum wire length for that net;
• on the computer, assigning first weights to nets whose estimated wire length value exceeds its maximum wire length value and assigning second weights, lower than the first weights, to nets whose estimated wire length value is less than its maximum wire length value;
• and,
• repeating the steps of placing, comparing and assigning until all nets have been placed in the integrated circuit layout design on the simulated integrated circuit.

A computer implemented method for designing an integrated circuit layout comprising the computer implemented steps of:

• statistically determining a predictive interconnect capacitance for different types of integrated circuit layout nets;
• calculating an average capacitance per unit wire length for the integrated circuit layout;
• converting the predictive interconnect capacitance for each different type of net into a maximum wire length value using the calculated average capacitance;
• placing at least one net at a desired location in an integrated circuit layout design, and estimating wire length of each net on the basis of the placement;
• comparing the estimated wire length of each net with the maximum wire length for that net;
• assigning first weights to nets whose estimated wire length value exceeds its maximum wire length value and assigning second weights, lower than the first weights, to nets whose estimated wire length value is less than its maximum wire length value;
• and,
• repeating the steps of placing, comparing and assigning until all nets have been placed in the integrated circuit layout design.