US RE35,613 EGranted

Dynamic random access memory with isolated well structure

AssigneeMitsubishi Denki Kabushiki Kaisha

InventorsKenichi Yasuda, Makoto Suwa, Shigeru Mori

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Abstract

A semiconductor memory device includes a first conductivity type well in a first conductivity type semiconductor substrate surrounded by a second conductivity type well, one of a memory cell and an external input circuit arranged on the first conductivity type well and the other disposed outside the second conductivity type well. A predetermined power supply voltage is applied to the second conductivity type well and the first conductivity type well is connected to ground. In the structure, charge carriers injected from the external input circuit are absorbed in the second conductivity type well. As a result, the charge carriers are prevented from reaching the memory cell and destroying data stored therein. Therefore, it is possible to miniaturize transistors and increase integration density of dynamic random access memory devices without degrading the source to drain dielectric strength.

Claims16

Dependent claims

A semiconductor memory device comprising:

a first conductivity type semiconductor substrate having a surface;
a first well of a first conductivity type disposed in said semiconductor substrate at the surface;
a second well of a second conductivity type and a third well of the second conductivity type, said second and third wells being disposed in said semiconductor substrate at the surface ..adjacent.!. , on opposite sides of, and contacting said first well;
a fourth well of the first conductivity type disposed in said semiconductor substrate at the surface within and surrounded by said third well;
a memory cell disposed on the surface of said semiconductor substrate within said fourth well;
a first transistor disposed on the surface of said semiconductor substrate within said first well;
and
a second transistor disposed on the surface of said semiconductor substrate within said second well, said first and second transistors connected for writing data into said memory cell and reading data out of said memory cell, said second and third wells for connection to a power supply voltage, and said first well and said semiconductor substrate for connection to ground.

5 more elements

A semiconductor memory device comprising:

a first conductivity type semiconductor substrate having a surface;
a first well of the first conductivity type disposed in said semiconductor substrate at the surface;
a second well of a second conductivity type and a third well of the second conductivity type disposed in said semiconductor substrate at the surface adjacent said first well;
a fourth well of the first conductivity type disposed at the surface of said semiconductor substrate within and surrounded by said third well;
a memory cell disposed on the surface of said semiconductor substrate within said first well;
an external input circuit disposed on the surface of said semiconductor substrate within said fourth well;
a first transistor disposed on the surface of said semiconductor substrate within said first well;
and
a second transistor disposed on the surface of said semiconductor substrate within said second well wherein said first and second transistors are connected for writing data into said memory cell and reading data out of said memory cell, said second and third wells for connection to a power supply voltage, and said first well and said semiconductor substrate for connection to ground.

6 more elements

Dependencies are inferred from the claim text.