Bit line and column circuitry used in a semiconductor memory

In a CMOS integrated circuit device, a memory array and control circuitry therefor comprising:

• a plurality of pairs of column lines, each pair constituting a bit line and a bit bar line;
• a plurality of work lines extending transverse to said pairs of column lines;
• a plurality of multi-transistor memory cells, each cell being located at an intersection of, and connected to, one word line and one pair of columns lines;
• a plurality of bias [means] circuits , each connected to one end of a corresponding column line, each [said] bias [means] circuit including a P-channel transistor and an N-channel transistor, each of said transistors having its source-drain path connected between a supply voltage and [the] a corresponding column line, each [said] bias [means being operative for limiting the current drain to the threshold level of said P-channel transistor] circuit being arranged to limit the voltage swing on the corresponding column line as the corresponding column line for the particular bias [means] circuit is pulled toward ground;
• and
• a voltage reference circuit having an output connected to the gates of the P-channel transistors for the bias [means] circuits for [column line pairs] said pairs of column lines , said reference circuit having transistor elements sized to mirror transistor elements of said bias [means] circuits and said memory cells and thereby compensate for [process variation within said] changes in the ambient conditions within the integrated circuit device.

In a CMOS integrated circuit device, a memory array and control circuitry therefor comprising:

• a plurality of pairs of bit lines;
• a plurality of word lines extending transverse to said pairs of bit lines;
• a plurality of multi-transistor memory cells, each cell including a pair of cross-coupled transistors and being located at an intersection of, and connected to, a corresponding pair of bit lines and a corrsponding word line;
• a plurality of bias circuits coupled to said bit lines, each one of said bit lines corresponding to a respective bias circuit, each [said] bias circuit including a P-channel transistor and an N-channel transistor coupled to each other and coupled between a supply voltage and the corresponding bit line, [said] each bias circuit providing a clamp and a current source for the bit line corresponding to [the] that bias circuit;
• and
• a voltage reference circuit coupled to said supply voltage and having an output coupled to the gate electrodes of said P-channel transistors in said plurality of bias circuits, said reference circuit reducing the effects of [process variations between elements of said] changes in the ambient conditions within the integrateed circuit device.