Textured metallic compression bonding
AssigneeAT&T Corp.
InventorsGreg E. Blonder, Theodore A. Fulton
Life of this patent
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Abstract
Integrated circuit chip-to-chip interconnections are made via gold pads on each chip that are bonded to corresponding gold pads on a silicon wafer chip carrier. The pads on the chips and/or the pads on the carrier are characterized by texturing (roughening) with a feature size of the order of a micrometer or less, so that each of the pads on the chip can be attached to each of the pads on the carrier by compression bonding at room temperature--i.e., cold-well bonding. In particular, the texturing of the gold pads on the silicon carrier is obtained by etching V-grooves locally on the surface of the underlying silicon carrier in the regions of the pads, thermally growing a silicon dioxide layer on the silicon career, and depositing the gold on the silicon dioxide layer.
Claims22
In combination
- (a) a semiconductor integrated circuit chip having an integrated circuit connected to a plurality of metallic chip pads located on a major surface of the chip;
- (b) a carrier upon which are located metallic wiring interconnections having metallic carrier pads that are compression bonded to the chip pads, each of either the carrier pads[,] or the chip pads, [or] but not both , having at least a portion thereof that is textured prior to bonding with indentations whose depths are[, or protrusions whose heights are,] of the order of one micrometer.
The combination of claim [10] 9 in which the surfaces of the chip pads are essentially [gold] gold .
In combination:
- a first body having a first metallic layer located contiguous with a first surface of the first body;
- and
- a second body having a second metallic layer being compression bonded to the second metallic layer, either the first metallic layer or the second metallic layer, but not both the first and second metallic layers, having at least a portion thereof that is textured prior to bonding with indentations whose depths are of the order of one micrometer or less.
The combination of 17 in which the wafer has a plurality of V-grooves at the portion thereof bonded to the second metallic layer.
Dependencies are inferred from the claim text.