Local interconnect process for integrated circuits
AssigneeSGS-Thomson Microelectronics S.A.
InventorsFu-Tai Liou, Yih-Shung Lin, Fusen E. Chen
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Abstract
A silicide layer, to improve conductivity, is formed over a first layer of polycrystalline silicon, followed by a second layer of polycrystalline silicon. This structure is then patterned to form gate regions over active areas. A layer of metal silicide is formed over the entire surface of the chip, and patterned to form local interconnect. Etching of the second metal silicide layer is stopped by the second polycrystalline silicon layer, thereby protecting the rust metal silicide layer from damage.
Claims18
A method for forming electrical interconnections in an integrated circuit, comprising the steps of:
- forming a gate oxide layer on a substrate;
- forming a gate polycrystalline silicon layer over the gate oxide layer,
- forming a first conductive layer including metal over the gate polycrystalline silicon layer;
- forming a conductive cap layer over the tint conductive layer including metal;
- patterning the gate oxide, gate polycrystalline silicon, first conductive layer including metal, and conductive cap layers to form gates over active regions in the substrate;
- forming sidewall insulating regions on the gates;
- forming a second conductive layer including metal over the integrated circuit;
- and
- patterning the second conductive layer including metal to form electrical interconnections, wherein the conductive cap layer protects the tint conductive layer from damage during such patterning step and wherein the second conductive layer makes electrical contact with the gates through the conductive cap layer, whereby electrical connections are made between the gates and the substrate through the second conductive layer.
A method for forming electrical interconnections in an integrated circuit,
- forming a gate oxide layer on a substrate;
- forming a gate polcrystalline silicon layer over the gate oxide layer;
- forming a first electrically conductive layer, containing a refractory metal material, over the gate polycrystalline silicon layer;
- forming a conductive cap layer over the first electrically conductive layer;
- patterning the gate oxide, gate polycrystalline silicon, electrically conductive layers, and conductive cap layers to form gates over active regions;
- forming sidewall insulating regions on the gates;
- forming a second electrically conductive layer, containing a refractory metal material, over the integrated circuit;
- and
- patterning the second electrically conductive layer to form electrical interconnections, wherein the conductive cap layer protects the first electrically conductive layer from damage during such patterning step, and wherein the second electrically conductive layer makes electrical contact with the gates through the conductive cap layer, whereby electrical connections are made between the gates and the substrate through the second electrically conductive layer.
Dependencies are inferred from the claim text.