US RE31,997 EGranted

Input-output unit for a microprocessor engine control system

AssigneeRobert Bosch GmbH

InventorWinfried Klotzner

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Abstract

Repetitive operations, such as fuel injection and/or ignition timing of a gasoline engine, are controlled by a microprocessor with reference to engine operation parameters that provide electrical inputs in a manner achieving increased efficiency and economy by the provision of an input-output unit that supplies considerable preprocessing of the input signals under control of the microprocessor through the usual data and address buses. Counters are operated to count down from count limit values. The counting rate, as well as the count limit values, are capable of being varied by commands through the data bus, from time to time, so as to make the capabilities of the system adaptable to a wide variety of particular engines. The system is readily programmable for a particular application or machine if a programmable read-only memory (PROM or EPROM) is used for programming the microprocessor.

Claims19

Dependent claims

In a system for controlling repetitive operations of a machine dependent on operating parameters such as the operation of electrical ignition in an internal combustion engine, which system comprises a microprocessor, a clock pulse generator, a read-only memory (ROM, PROM), a random access memory (RAM), a data bus and an address bus, both interconnecting said microprocessor with said read-only memory and said random access memory, and read and write enable connections for enabling the reading of said memories and writing into said random access memory the data on said data bus at the memory address specified on the said address bus,

an input-output unit for said system connected to said address bus and read and write connections including a decoding circuit, connected to said data bus, and connected to said microprocessor also through "clear" and "interrupt" connections for receiving a clearing command from said microprocessor and for providing an interrupt to said microprocessor, said input-output unit comprising:
a counter (61) for counting shaft rotation rate dependent signals arranged for operation in successive counting invervals, the length of which intervals are determined by setting of said counter through said data bus (14), and the position in time of which intervals is controlled by at least one timing reference mark of said machine, said counter having a multibit count state output and having input connections for having a count value set therein for initiation of counting and termination of and for counting said signals;
a comparator (64) and a buffer store (68) therefor, said comparator having one multibit comparison input connected to the count-state output of said counter (61) and its other multibit comparison input connected to said buffer store (68), and having an output for indicating at least one comparison condition of signals at said inputs thereof, said buffer being arranged to have its content written through said data bus;
a selectable multi-channel final stage array (75, 76, 49, 50) and providing a plurality of output command channels,
and select logic circuits (72, 73) for sequential preselection of said channels of said final stage array, said select logic circuits being connected to said data bus for their control and to said final stage array for channel preselection in response to a signal of a control signal sequence (F) and including circuits for transferring timed signals (E) obtained in response to the output of said comparator to the channels preselected in sequence,
said decoding circuit (100) being constituted so as to provide stepwise control of the various circuit components connected with said data bus (14) as selected over said address bus (15).

3 more elements

In a system for controlling repetitive operations of a machine dependent on operating parameters, such as the operation of electrical ignition in an internal combustion engine, which system comprises a microprocessor, a clock pulse generator, a read-only memory (ROM, PROM), a random access memory (RAM), a data bus and an address bus, both interconnecting said microprocessor with said read-only memory and said random access memory, and read and write enable connections for enabling the reading of said memories and writing into said random access memory the data on said data bus at the memory address specified on the said address bus,

an input-output unit for said system connected to said address bus and read and write connections including a decoding circuit (100), connected to said data bus, and connected to said microprocessor also through "clear" and "interrupt" connections for receiving a clearing command from said microprocessor and for providing an interrupt to said microprocessor, said input-output unit comprising:
means for communicating reference mark signals (B) derived from operation of said machine to said microprocessor through said data bus (14) for synchronizing signals of a control signal sequence (F) determined by said microprocessor and furnished to said decoding circuit (100) of said input-output unit through said data bus (14),
said decoding circuit (100) being constituted so as to provide stepwise control of the various circuit components connected with said data bus (14) as selected over said address bus (15);
a timing circuit (85,88) comprising a first counter for counting at a predetermined counting frequency and arranged for being supplied a count content from said data bus (14) in response to an enabling signal from an output (87) of said decoding circuit (100) for use of said count content as a number from which down counting is performed by said counter;
a second counter (112) which is arranged for being supplied with at least one magnitude value of an operating parameter of said machine in the form of a frequency supplied as a counting frequency and which is arranged to have its counting time prescribed by said timing circuit (85,88), and furthermore, is arranged so that its count result is transferable through a gate stage (113) to said data bus (14), and
a frequency selection decoder stage (119) and a frequency selecting circuit (117) controlled through said frequency selection decoder stage in response to an output (74) of said decoding circuit (100), whereby said predetermined counting frequency is subject to being varied over said data bus.

3 more elements

Dependencies are inferred from the claim text.