Non-volatile memory devices fabricated from graded or stepped energy band gap insulator MIM or MIS structure

A stepped insulator metal-silicon dioxide-silicon SIMOS FET structure having an injection region adjacent to the gate electrode, said injection region comprising a thin stepped band gap insulator adjacent to a relatively thick silicon dioxide insulator layer having embedded therein a layer of impurity atoms.

An improved graded oxide metal-silicon dioxide silicon GIMOS FET structure having an injection region adjacent to the gate electrode, said injection region comprising a thin graded band gap, said improvement being a layer of impurity atoms embedded in an oxide layer adjacent to the silicon substrate.

In a MOS FET device for performing a memory function said device being of the type comprising a silicon substrate having source and drain regions formed therein and an insulated gate structure formed between said source and drain regions, and wherein the band gap of the insulator of the insulated gate structure is reduced near the gate electrical contact interface to provide an injection region wherein holes or electrons depending on voltage bias, can be injected into the insulator under low to moderate electric field conditions from the gate electrical contact while simultaneously, electron or hole injection from the substrate interface is blocked due to the large insulator band gap at this interface, the improvement being a layer of impurity atoms embedded in said gate oxide proximate to the oxide-silicon interface for capturing and storing injected electrons or holes with high efficiency.

A metal-insulator-metal or metal-insulator-semiconductor structure, wherein the band gap of the insulator layer at its first interface only is reduced to provide an injection region where holes or electrons depending on voltage bias, can be injected into the insulator under low to moderate electrical field conditions from the contact at this interface while, simultaneously, electron or hole injection from said insulator's second interface is blocked due to the large insulator band gap near said second interface, the improvement being a floating polycrystalline silicon charge storage layer in said insulator near its second interface for capturing and storing injected electrons or holes with high efficiency.

A stepped insulator metal-silicon dioxide-silicon SIMOS FET structure having an injection region adjacent to the gate electrode, said injection region comprising a thin stepped band gap insulator, adjacent to a relatively thick silicon dioxide insulator layer having a floating polycrystalline silicon charge storage layer therein.

An improved graded oxide metal-silicon dioxide silicon GIMOS FET structure having an injection region adjacent to the gate electrode, said injection region comprising a thin graded band gap insulator, said improvement being a floating polycrystalline silicon charge storage layer in an oxide layer adjacent to the silicon substrate.

A metal-insulator-metal or metal-insulator-semiconductor structure, wherein the insulator has disposed thereon at its first interface, at least one relatively thin successive oxide layer, each successive oxide layer containing an increasing silicon content which provides an injection region where holes or electrons depending on voltage bias, can be injected into the insulator under low to moderate electrical field conditions from the contact at this first interface, while, simultaneously electron or hole injection from said insulator's second interface is blocked, the improvement being a charge trapping layer embedded in said insulator near its second interface for capturing and storing injected electrons or holes with high efficiency.

In a MOSFET device for performing a memory function said device being of the type comprising a silicon substrate having source and drain regions formed therein and an insulated gate structure formed between said source and drain regions and wherein said insulator comprises a relatively thick oxide layer over which is deposited at least one relatively thin successive oxide layer, each successively deposited oxide layer containing an increasing silicon content to provide an injection region wherein holes or electrons depending on voltage bias, can be injected into the insulator under low to moderate electric field conditions from the gate electrical contact which simultaneously, electron or hole injection from the substrate interface is blocked, the improvement being a layer of impurity atoms embedded in said oxide proximate to the oxide-silicon interface for capturing and storing injected electrons or holes with high efficiency.