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US RE31,079 EGranted
Method for manufacturing complementary insulated gate field effect transistors
AssigneeHitachi, Ltd.
InventorsKouichi Nagasawa, Yasunobu Kosa, Satoshi Meguro
Life of this patent
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Abstract
Method for manufacturing semiconductor devices including, e.g., complementary insulated gate field effect transistors of LOCOS (local oxidation of silicon) structure wherein after the formation of a well layer, an impurity having higher doping level than and the same conductivity type as a semiconductor substrate (well layer) is ion implanted at an area in the semiconductor substrate on which a field oxide layer is to be formed using an oxidation-resistive material, e.g. a silicon nitride layer , as a mask, and the semiconductor substrate surface is selectively thermally oxidized using the silicon nitride layer as a mask.
Claims29
A method for manufacturing complementary insulated gate field effect transistors comprising the steps of:
- (a) delimiting a portion of a surface of a semiconductor substrate of a first conductivity type and forming therein a well layer of a second conductivity type, forming a thin insulating layer over the entire surface thereof and then forming a silicon nitride layer over the entire surface thereof;
- (b) etching away said silicon nitride layer at least [those areas on] in an area in which a field oxide [layers are] layer is to be formed;
- (c) introducing an impurity of the second conductivity type at that area in said well layer of the second conductivity type on which the field oxide layer is to be formed;
- (d) heat treating the substrate to selectively thermally oxidize the areas on which the field oxide [layers are] layer is to be formed, using said silicon nitride layer as a mask to form a thick field oxide layer;
- and
- (e) removing the silicon nitride layer and the underlying thin insulating layer formed in said step (a), selectively forming gate insulation layers and silicon layers on the exposed substrate and well layer, and forming source regions and drain regions of [MIS devices] insulated gate field effect transistors in said semiconductor substrate of the first conductivity type and the well layer of the second conductivity type using said silicon layers and said thick field oxide [layers] layer as masks[, and forming diffusion layers of desired impurity concentrations beneath said thick field oxide layers].
3 more elements
A method for manufacturing complementary insulated gate field effect transistors comprising the steps of:
- (a) delimiting a portion of a surface of an N-type semiconductor substrate and forming a P-type well layer therein, forming a thin thermal oxidation layer over the surface thereof and then forming a silicon nitride [film] layer over the surface thereof;
- (b) etching away said silicon nitride layer at those areas on which a field oxide [layers are] layer is to be formed;
- (c) ion implanting donor and acceptor impurities into those areas in said N-type semiconductor substrate and the P-type well layer, respectively, on which the field oxide [layers are] layer is to be formed, using a portion of said silicon nitride layer as a mask;
- (d) heat treating the substrate to selectively thermally oxidize those areas on which the field oxide [layers are] layer is to be formed, using said silicon nitride layer as a mask for forming the field oxide [layers] layer of LOCOS structure;
- and
- (e) removing said silicon nitride layer and the underlying thin thermal oxidation layer formed in said step (a), selectively forming gate insulation layers and semiconductor layers on the exposed N-type substrate and exposed P-type well layer, forming source regions and drain regions of [MIS devices] insulated gate field effect transistors in said N-type semiconductor substrate and said P-type well layer using said semiconductor layers and said field oxide [layers] layer as masks.
3 more elements
A method for manufacturing complementary insulated gate field effect transistors comprising the steps of:
- (a) delimiting a portion of a surface of an N(P)-type semiconductor substrate and forming a P(N)-type well layer therein, forming a thin thermal oxidation layer over the entire surface thereon, and then forming a silicon nitride layer over the entire surface thereof;
- (b) etching away said silicon nitride layer and the underlying thin thermal oxidation layer at those areas on which a field oxide [layers are] layer is to be formed;
- (c) ion implanting [acceptor (donor) or] donor (acceptor) impurity in the exposed surface area of the substrate [in the area of N(P) channel of P(N) channel device];
- (d) ion implanting [donor (acceptor) or] acceptor (donor) impurity in the exposed surface area [of the substrate in the area of P(N) channel of N(P)channel device] of the well layer ;
- (e) heat treating the substrate to selectively thermally oxidize the exposed surface areas of the substrate and the well layer using said silicon nitride layer as a mask to form a thick field oxide [layers] layer ;
- and
- (f) removing the silicon nitride layer and the underlying thin thermal oxidation layer formed in the step (a), selectively forming gate insulation layers and silicon layers on the exposed surface area of the substrate and well layer, and forming source regions and drain regions of the respective [MIS devices] insulated gate field effect transistors using said silicon layers and said thick field oxide [layers] layer as masks[, and forming diffusion layers of desired impurity concentrations under said field oxide layers].
4 more elements
A method for manufacturing a semiconductor integrated circuit device including complementary insulated gate field effect transistors comprising the steps of:
- (a) delimiting a portion of a surface of an N-type silicon substrate and forming a P-type well layer therein by ion implantation, forming a silicon dioxide layer over the entire surface thereof and then forming a silicon nitride layer over the entire surface thereof;
- (b) selectively forming a first photoresist layer on said silicon nitride layer over said N-type silicon substrate and said P-type well layer;
- (c) etching away said silicon nitride layer and the underlying silicon [nitride] dioxide layer using said first photoresist layer as a mask to expose surfaces of said N-type silicon substrate and said P-type well layer;
- (d) covering the exposed N-type silicon substrate surface with a second photoresist layer;
- (e) ion implanting an acceptor impurity into the exposed surface area of said P-type well layer using said first photoresist layer as a mask;
- (f) removing said first and second photoresist layers and covering the exposed surface of said P-type well layer with a third photoresist layer;
- (g) ion implanting a donor impurity into the exposed surface area of said N-type silicon substrate using said silicon nitride as mask;
- (h) removing said third photoresist film and selectively thermally oxidizing the exposed surfaces of said P-type well layer and said N-type silicon substrate using said silicon nitride layer as a a mask to form a thick field silicon dioxide [layers] layer ;
- (i) etching away said silicon nitride layer and the underlying silicon dioxide layer to expose said P-type well layer and said N-type silicon substrate;
- (j) oxidizing the exposed surfaces of said P-type well layer and said N-type silicon substrate to form gate silicon dioxide layers;
- (k) forming a silicon [layers] layer over the entire surfaces of said field silicon dioxide [layers] layer and said gate silicon dioxide layers;
- (l) selectively etching away said silicon [layers] layer and said gate silicon dioxide layers to expose the surfaces of said N-type silicon substrate and said P-type well layer;
- (m) diffusing an acceptor impurity into the exposed N-type silicon substrate and a donor impurity into the exposed P-type well layer using the remaining silicon layer and said field silicon dioxide [layers] layer as masks to form source regions and drain regions, respectively, and
- (n) connecting aluminum layers to said source regions and drain regions formed in said N-type silicon substrate and said P-type well layer, respectively.
11 more elements
A method for manufacturing a semiconductor device including insulated gate field effect transistors, comprising the steps of:
- (a) forming a silicon substrate containing a well region of one conductivity type extending to a major surface of the substrate, and a substrate region of another conductivity type adjoining said well region and extending to said major surface;
- (b) covering said major surface of the substrate with an oxidation-resistive material to cover selected surface areas of said well and substrate regions and leave other surface area portions of said well and substrate regions uncovered with said oxidation-resistive material;
- (c) introducing a first impurity determining said one conductivity type into the uncovered surface area portions of said well region;
- (d) subjecting the combination thus obtained to an oxidation treatment to selectively oxidize portions of said substrate which are not covered with said oxidation-resistive material thereby to form a relatively thick silicon oxide layer having a plurality of openings at said selected surface areas;
- (e) removing said oxidation-resistive material from said substrate;
- (f) forming relatively thin silicon oxide layers on said selected surface areas in said openings;
- and
- (g) forming at said selected surface areas in said openings insulated gate field effect transistors using said relatively thin silicon oxide layers as gate insulators.
5 more elements
A method for manufacturing a semiconductor integrated circuit device including circuit elements, comprising the steps of:
- (a) forming a silicon substrate containing a well region of one conductivity type extending to a major surface of the substrate and a substrate region of another conductivity type adjoining said well region and extending to said major surface;
- (b) covering said major surface of the substrate with an oxidation-resistive mask, said mask having a plurality of islands of an oxidation-resistive material which cover the surface of said well region other than selected surface areas in the midst, as well as in the periphery, of the surface of the well region;
- (c) introducing an impurity determining said one conductivity type into the selected surface areas of said well region;
- (d) subjecting the combination thus obtained to an oxidation treatment to selectively oxidize portions of said major surface of the silicon substrate which are not covered with said mask, thereby to form a relatively thick silicon oxide layer which includes a plurality of first openings located at portions of said well region corresponding to said islands of said oxidation-resistive material and second openings located on the surface of said substrate region;
- (e) removing said oxidation-resistive mask from the major surface of said substrate;
- (f) forming relatively thin silicon oxide layers covering the surface portions of said well and substrate regions at said first and second openings;
- and
- (g) forming circuit elements at surface portions of said well and substrate
- regions in said first and second openings.
6 more elements
A method for manufacturing a semiconductor device including insulated gate field effect transistors, comprising the steps of:
- (a) forming a silicon substrate containing a well region of one conductivity type extending to a major surface of the substrate, and a substrate region of another conductivity type adjoining said well region, underlying said well region and extending to said major surface;
- (b) covering said major surface of the substrate with an oxidation-resistive material to cover selected areas of said well and substrate regions;
- (c) introducing an impurity determining said other conductivity type into the selected surface areas of said substrate region;
- (d) subjecting the combination thus obtained to an oxidation treatment to selectively oxidize portions of said substrate and well regions which are not covered with said oxidation-resistive material so as to form a relatively thick silicon oxide layer having a plurality of openings at said selected surface areas and so as not to reach portions of said substrate region underlying said well region;
- (e) removing said oxidation-resistive material from said substrate;
- (f) forming relatively thin silicon oxide layers on said selected surface areas in said openings;
- and
- (g) forming at said selected surface areas in said openings insulated gate field effect transistors using said relatively thin silicon oxide layers
- as gate insulators.
6 more elements
Dependencies are inferred from the claim text.