Monostable multivibrator
AssigneeTrio Kabushiki Kaisha
InventorYukihiko Miyamoto
Life of this patent
Estimating the term…
Abstract
A monostable multivibrator including a gate circuit, a time constant circuit, and an inverter circuit. An input signal to the gate circuit causes the time constant circuit which preferably includes a resistor and a capacitor to charge or discharge. A signal derived from the time constant circuit is applied to an input bias circuit including an emitter follower type transistor circuit associated with a differential amplifier within the inverter circuit to control the duration of the monostable output pulse.
Claims7
In a monostable multivibrator having a gate circuit, a time constant circuit connected to the gate circuit, and an inverter circuit, the improvement wherein said inverter circuit comprises a differential amplifier having two inputs and having an input bias circuit including a pair of transistors each biased connected as an emitter follower, the emitters of said pair of transistors connected are each to respective inputs of said differential amplifier, the bases of said transistors respectively connected to first and second bias means, and the emitter of one of said transistors additionally connected to the time constant circuit.
A monostable multivibrator comprising;
- a gate circuit;
- a time constant circuit including a capacitor and a resistor, said capacitor being connected at one end to said gate circuit and at the other end to one end of said resistor, the other end of which is adapted to be operably connected to the positive side of a power source;
- an inverter circuit including first, second, third, and fourth transistors, the collectors of said first and second transistors being adapted to be operably connected to the positive side of a power source, the emitters of said first and second transistors being connected to each other and being adapted to be operably connected to the negative side of a power source, said third and fourth transistors being connected in emitter follower circuit arrangements, the collector of said first transistor also being operably connected to said gate circuit and to a first output terminal, the base of said first transistor being connected to the emitter of said third transistor, the collector of said third transistor being adapted to be connected to the negative side of a power source, the emitter of said third transistor also being connected to the connection point between said capacitor and said resistor, the collector of said second transistor being connected to a second output terminal and the base of said second transistor being connected to the emitter of said fourth transistor, and the collector of said fourth transistor being adapted to be connected to the negative side of a power source;
- and
- first and second bias means, the base of said third transistor being connected to said first bias means, and the base of said fourth transistor being connected to said second bias means.
Dependencies are inferred from the claim text.