PLL post divider phase continuity
AssigneeQUALCOMM Incorporated
InventorsJingcheng Zhuang, Jianyun Hu, Animesh Paul, Xinhua Chen, Frederic Bossu
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Abstract
A phase continuity architecture is provided to maintain the phase continuity for a post divider output signal from a post divider that post divides a PLL output signal. A pulse swallower removes a pulse from the PLL output signal responsive to an edge is a divided feedback clock signal. A sampler samples the post divider output signal responsive to a detection of the missing pulse to determine a phase relationship between the post divider output signal and the divided feedback clock signal.
Claims20
A system, comprising:
- a feedback divider for a fractional-N phase-locked loop (PLL), wherein the feedback divider is configured to divide a PLL output signal for the fractional-N PLL to form a divided feedback clock signal;
- a pulse swallower circuit configured to remove a pulse from the PLL output signal responsive to an edge for the divided feedback clock signal to form a modified PLL output signal having a missing pulse;
- a post divider for post dividing the modified PLL output signal to form a post divided output signal;
- a clock recovery circuit configured to assert a recovered divided feedback clock signal responsive to the missing pulse in the modified PLL output signal;
- and
- a sampling circuit configured to sample the post divided output signal responsive to the assertion of the recovered divided feedback clock signal.
A method of sampling the phase of a post divided output signal, comprising:
- removing a pulse from a phase-locked loop (PLL) output signal for a fractional-N PLL responsive to an edge of a divided feedback clock signal to form a modified PLL output signal having a missing pulse;
- dividing the modified PLL output signal in a post divider to form the post divided output signal;
- and
- at a first time, sampling the post divided output signal responsive to a detection of the missing pulse in the modified PLL output signal to determine a first phase relationship between the post divided output signal and the divided feedback clock signal.
A system, comprising:
- a feedback divider for a fractional-N phase-locked loop (PLL), wherein the feedback divider is configured to divide a PLL output signal from the fractional-N PLL to form a divided feedback clock signal;
- a pulse swallower circuit configured to remove a pulse from the PLL output signal responsive to an edge for the divided feedback clock signal to form a modified PLL output signal with a missing pulse;
- a post divider for post dividing the modified PLL output signal to form a post divided output signal;
- and
- means for sampling the post divided output signal responsive to the missing pulse in modified PLL output signal to determine a phase relationship between the post divided output signal and the divided feedback clock signal.
Dependencies are inferred from the claim text.