Methods of forming a nano-sheet transistor device with a thicker gate stack and the resulting device

A method of forming a nano-sheet transistor, comprising:

• forming a patterned stack of materials above a semiconductor substrate, said patterned stack of materials comprising alternating layers of channel semiconductor material and sacrificial semiconductor material layers, wherein an initial thickness of each of said channel semiconductor material layers is at least 1.5-3 times greater than an initial thickness of each of said sacrificial semiconductor material layers;
• forming a replacement gate cavity above said patterned stack of materials;
• performing at least one first etching process through said replacement gate cavity to selectively remove at least a portion of said sacrificial semiconductor material layers exposed by the formation of said replacement gate cavity relative to said layers of channel semiconductor material;
• performing at least one second etching process through said replacement gate cavity to reduce said initial thickness of a portion of each of said layers of channel semiconductor material exposed by the removal of the at least a portion of the sacrificial semiconductor material layers to thereby produce a reduced-thickness portion of each of said layers of channel semiconductor material, wherein said reduced-thickness portion of each of said layers of channel semiconductor material has a final thickness that is about 25-50% less than said initial thickness of said layers of channel semiconductor material;
• and
• forming a replacement gate structure within said replacement gate cavity and around at least said reduced-thickness portions of said layers of channel semiconductor material.

A nano-sheet transistor, comprising:

• a gate structure;
• a sidewall spacer positioned adjacent said gate structure;
• and
• a channel semiconductor material layer, said channel semiconductor material layer comprising:
• first and second portions and a reduced-thickness portion positioned laterally between said first and second portions, wherein said first and second portions have an initial thickness and the reduced-thickness portion has a final thickness that is less than said initial thickness and wherein at least a portion of said reduced-thickness portion is positioned vertically under said gate structure and at least a portion of each of said first and second portions is positioned vertically under said sidewall spacer and wherein said gate structure is positioned around at least a portion of said reduced-thickness portion of said channel semiconductor material layer.