Methods of forming an isolated nano-sheet transistor device and the resulting device

A method of forming a nano-sheet transistor comprising source/drain areas where source/drain regions will be formed, the method comprising:

• forming a sacrificial gate above a fin-like configured stack of materials, said sacrificial gate comprising a sacrificial gate structure with a gate cap positioned above said sacrificial gate structure and a sidewall spacer positioned adjacent said sacrificial gate structure and said gate cap, said stack of materials comprising a first layer of a first sacrificial material positioned above a semiconductor substrate, at least one channel semiconductor material layer and a plurality of second layers of a second sacrificial material, wherein a lowermost of said plurality of second layers is positioned between said first layer and a lowermost of said at least one channel semiconductor material layer;
• patterning all of said layers in said stack of materials above said lowermost of said plurality of second layers using said sacrificial gate as an etch mask while leaving said lowermost of said plurality of second layers in position above said source/drain areas;
• forming a trench in each of said source/drain areas, wherein each trench extends from a first opening in said lowermost of said plurality of second layers and into said semiconductor substrate, said first layer being exposed within each trench;
• performing an isotropic etching process through said first opening to selectively remove substantially all of said first layer and thereby define an empty space located above said semiconductor substrate and below said lowermost of said plurality of second layers and said sacrificial gate, said empty space being in communication with said trenches;
• performing a conformal deposition process so as to deposit a conformal layer of a device isolation material adjacent at least said sacrificial gate while at least partially filling said empty space with said device isolation material and substantially filling said first opening with said device isolation material;
• and
• performing a recess etching process to remove at least portions of said conformal layer of said device isolating material positioned above said first opening and thereby define a recessed upper surface of said device isolation material.

A method of forming a nano-sheet transistor comprising source/drain areas where source/drain regions will be formed, the method comprising:

• forming a sacrificial gate above a fin-like configured stack of materials, said sacrificial gate comprising a sacrificial gate structure with a gate cap positioned above said sacrificial gate structure and a sidewall spacer positioned adjacent said sacrificial gate structure and said gate cap, said stack of materials comprising a first layer of a first sacrificial material positioned above a semiconductor substrate, at least one channel semiconductor material layer and a plurality of second layers of a second sacrificial material, wherein a lowermost of said plurality of second layers is positioned between said first layer and a lowermost of said at least one channel semiconductor material layer;
• patterning all of said layers in said stack of materials above said lowermost of said plurality of second layers using said sacrificial gate as an etch mask while leaving said lowermost of said plurality of second layers in position above said source/drain areas;
• forming a sacrificial sidewall spacer adjacent said sidewall spacer of said sacrificial gate and above portions of said lowermost of said plurality of second layers positioned above said source/drain areas;
• performing an etching process using said sacrificial sidewall spacer as a portion of an etch mask so as to remove at least portions of said lowermost of said plurality of second layers positioned above said source/drain areas;
• with said sacrificial sidewall spacer in position, performing at least one etching process to form a trench in each of said source/drain areas, wherein each trench extends form a first opening in said lowermost of said plurality of second layers and into said semiconductor substrate, said first layer being exposed within each trench;
• performing an isotropic etching process through said first opening to selectively remove substantially all of said first layer and thereby define an empty space located above said semiconductor substrate and below said lowermost of said plurality of second layers, said empty space being in communication with said trenches;
• performing a conformal deposition process so as to deposit a conformal layer of a device isolation material adjacent at least said sacrificial gate while at least partially filling said empty space with said device isolation material and substantially filling said first opening with said device isolation material;
• and
• performing a recess etching process to remove at least portions of said conformal layer of said device isolation material positioned above said first opening and thereby define a recessed upper surface of said device isolation material.