Low-power and low-latency device enumeration with cartesian addressing

A system, comprising:

• a host device including a host master interface connected to a first point-to-point (P2P) link having a first link ID, the host device further including a node aggregator comprising a processor, wherein the host device is configured to concatenate a master bit to the first link ID to form a node identification (ID) for the host master interface;
• a first slave device including a first slave interface connected to the first P2P link, the first slave device further including a slave master interface connected to a second P2P link having a second link ID, wherein the first slave device is configured to concatenate a slave bit to the first link ID to form a node ID for the first slave interface and to concatenate a master bit to the second link ID to form a node ID for the slave master interface;
• and
• a second slave device including a second slave interface connected to the second P2P link, wherein the second slave device is configured to concatenate a slave bit to the second link ID to form a node ID for the second slave interface;
• wherein the node aggregator is configured to assign a host-facing address for the second slave device that is a concatenation of the node ID for the second slave interface, the node ID for the master slave interface, the node ID for the first slave interface, and the node ID for the host master interface and to assign a host-facing address for the first slave device that is a concatenation of the node ID for the first slave interface and the node ID for the host master interface, and wherein the node aggregator is further configured to address each slave device with a message including the slave device's host-facing address, the message including a bit-optimized address to be assigned to the slave device, the bit-optimized address for each slave device being shorter than the host-facing address for each slave device.