Low power high speed interface
AssigneeTelefonaktiebolaget LM Ericsson (publ)
InventorFenghao Mu
Life of this patent
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Abstract
An interface for inter-chip communication, comprises a transmitter part (TX) for transmitting a differential signal and a receiver part (RX) for receiving the differential signal, the transmitter part (TX) being provided in a first integrated circuit chip (CHIP A) and the receiver part (RX) being provided in a second integrated circuit chip (CHIP B). The transmitter part (TX) comprises a first transistor (Tx1) and a second transistor (Tx2) arranged in a common source configuration, and the receiver part (RX) comprises a third transistor (TR1) and a fourth transistor (TR2) arranged in a common gate configuration. Current flowing in the receiver part (RX) also flows through the transmitter part (TX).
Claims14
An interface for inter-chip communication, comprising:
- a transmitter circuit configured to transmit a differential signal and a receiver circuit configured to receive the differential signal, the transmitter circuit being provided in a first integrated circuit chip and the receiver circuit being provided in a second integrated circuit chip;
- wherein the transmitter circuit comprises:
- a first transmitter input for an input binary signal and a second transmitter input for the complement of the input binary signal;
- a first transmitter output for a first part of the differential signal and a second transmitter output for a second, complementary part of the differential signal;
- a first transistor having a first gate coupled to the first transmitter input, a first source coupled to a first node, and a first drain coupled to the first transmitter output;
- a second transistor having a second gate coupled to the second transmitter input, a second source coupled to the first node, and a second drain coupled to the second transmitter output;
- and
- wherein the first node is coupled to a first voltage rail by means of a first coupling element;
- and
- wherein the receiver circuit comprises:
- a first receiver input coupled to the first transmitter output for receiving the first part of the differential signal and a second receiver input coupled to the second transmitter output for receiving the second, complementary part of the differential signal;
- a first receiver output for an output binary signal and a second receiver output for the complement of the output binary signal;
- a third transistor having a third gate coupled to a first bias voltage, a third source coupled to the first receiver input, a third drain coupled to the first receiver output, the third drain also coupled to a second voltage rail by means of a first inductive load;
- and
- a fourth transistor having a fourth gate coupled to the first bias voltage, a fourth source coupled to the second receiver input, a fourth drain coupled to the second receiver output, the fourth drain also coupled to the second voltage rail by means of a second inductive load.
Dependencies are inferred from the claim text.