Multi-petascale highly efficient parallel supercomputer

A scalable, parallel computing system comprising:

• a plurality of processing nodes interconnected by independent networks, each processing node including one or more processing elements, said elements including one or more processor cores, and a direct memory access (DMA) for performing computation or communication activity as required when performing parallel algorithm operations;
• a first independent network comprising an n-dimensional torus network, where n is an integer greater than or equal to 5, including communication links interconnecting said processing nodes in a manner optimized for providing point-to-point and multicast packet communications among said processing nodes or sub-sets of processing nodes of said network;
• a plurality of Input/Output (I/O) nodes, a second independent network including an external network connecting each I/O node to other processing nodes;
• wherein sub-sets of processing nodes are interconnected by divisible portions of said first and second networks for dynamically configuring one or more combinations of independent processing networks according to needs of one or more algorithms,
• wherein each of said configured independent processing networks is utilized to enable simultaneous collaborative processing for optimizing algorithm processing performance, and
• wherein each said processing element is multi-way hardware threaded supporting transactional memory execution and thread level speculation, wherein said plurality of processing elements are configured to run speculative threads in parallel,
• a cache memory associated with each said processing element at each node, said associated cache memory including a second level (L2) cache supporting thread-level speculative operations (TLS), said TLS operations handling multiple versions of data, and
• a DMA (direct memory access) network interface for transferring data to/from a cache memory, said DMA interface enabling internode communications that overlap with computations running concurrently on the nodes,
• wherein a processing element retrieves data by issuing a command and passing the command to each of a stream prefetch engine and a list prefetch engine, the stream prefetch engine and the list prefetch engine for prefetching data to be needed in subsequent clock cycles in the processor in response to the passed command, wherein the stream prefetch engine and the list prefetch engine work simultaneously;
• and
• a single prefetch data array for storing the addresses associated with prefetch requests that have been previously issued by the one or more simultaneously operating prefetch engines, wherein the stream prefetch engine is configured to:
• determine a slowest data or instruction stream and a fastest data or instruction stream, based on speeds of data or instruction streams processed by the hardware processor, wherein a fast data stream includes data which is requested by the hardware processor but not resident in said single prefetch data array;
• decrease a prefetching depth of the slowest data or instruction stream, the prefetching depth referring to a specific amount of data or instructions to be prefetched;
• and
• increase the prefetching depth of the fastest data or instruction stream by the decreased prefetching depth of the slowest data or instruction stream.