Pipelined systolic finite impulse response filter

A method for configuring a systolic FIR filter circuit, comprising:

• using an input sample chain to provide first, second, third, and fourth samples at first, second, third, and fourth sample points, respectively;
• configuring a first tap circuit to compute a first tap output based on the first and second samples;
• configuring a second tap circuit to compute a second tap output based on the third and fourth samples;
• and
• selecting a first number of delays and a second number of delays, wherein the second number of delays is smaller than the first number of delays, wherein the first number of delays separates the second and fourth sample points, and wherein the second number of delays separates the first and second tap circuits in an output cascade chain.

A systolic FIR filter circuit comprising:

• an input sample chain having a first leg, a second leg, and an input at a point between the first and second legs;
• a first sample point in the first leg that is separated from the input by a first number of sample delays;
• a second sample point in the second leg that is separated from the input by a second number of sample delays, wherein the difference between the second number of sample delays and first number of sample delays is an even number of sample delays;
• and
• a FIR filter tap circuit that combines a first sample from the first sample point with a second sample from the second sample point to produce a tap output.