Matrix multiply accumulate instruction

An apparatus comprising:

• a plurality of data registers;
• and
• a decode unit to decode an instruction, wherein the instruction includes a field to identify for a first register to store a 8×8 matrix organized into 64-bit sections of 8 byte rows, a field to identify for a second register to store a 8×8 matrix organized into 64-bit sections of 8 byte rows, a field to identify a second packed data register to store multiplicative constants as an 8×8 matrix, a field to identify a third register, and an immediate representing up to an 8 degree polynomial and the multiplication is reduced with respect to this polynomial;
• an execution unit coupled with the plurality of the data registers, to execute the decoded instruction to:
• iteratively perform for each position in a result matrix stored in the third register,
• a multiply of a first value at a matrix position stored in the first register with a value at a matrix position stored in the second register to obtain a first multiplicative value, the first multiplicative value having a larger bit width than a bit width of the first value, wherein the positions in the first register and the second register are determined by the position in the result matrix,
• a reduction operation to obtain a reduced multiplicative value having a bit width equal to the bit width of the first register, wherein the reduction operation comprises to perform a reduction operation on the multiplicative value with respect to the polynomial term of the immediate prior to performing the XOR operation, and
• an exclusive or (XOR) operation with the reduced multiplicative value and a value stored at a result matrix position stored in the third register to obtain a result value.

A system comprising:

• an interconnect;
• a processor coupled with the interconnect, to execute an instruction to iteratively perform for each position in a result matrix stored in a third register to perform a multiply of a first value at a matrix position stored in a first register with a value at a matrix position stored in a second register to obtain a first multiplicative value, the first multiplicative value having a larger bit width than that of the first value, wherein the positions in the first register and the second register are determined by the position in the result matrix, a reduction operation to obtain a reduced multiplicative produce having a bit width equal to the bit width of the first register;
• an exclusive or (XOR) operation with the reduced multiplicative value and a value stored at a result matrix position stored in the third register to obtain a result value, wherein the instruction includes a field to identify for the first register to store a 8×8 matrix organized into 64-bit sections of 8 byte rows, a field to identify for the second register to store a 8×8 matrix organized into 64-bit sections of 8 byte rows, a field to identify a second packed data register to store multiplicative constants as an 8×8 matrix, a field to identify the third register, and an immediate representing up to an 8 degree polynomial, and wherein the reduction operation is to perform a reduction operation on the multiplicative value with respect to the polynomial term of the immediate prior to performing the XOR operation;
• and
• a dynamic random access memory (DRAM) coupled with the interconnect.

An article of manufacture comprising:

• a non-transitory machine-readable storage medium including one or more solid data storage materials, the machine-readable storage medium storing an instruction including a field to identify for a first register to store a 8×8 matrix organized into 64-bit sections of 8 byte rows, a field to identify for a second register to store a 8×8 matrix organized into 64-bit sections of 8 byte rows, a field to identify a second packed data register to store multiplicative constants as an 8×8 matrix, a field to identify a third register, and an immediate representing up to an 8 degree polynomial, which when executed causes a processor to:
• iteratively perform for each position in a result matrix stored in the third register:
• a multiply of a value at a matrix position stored in the first register with a value at a matrix position stored in the second register to obtain a first multiplicative value, the first multiplicative value having a larger bit width than that of the first value, wherein the positions in the first register and the second register are determined by the position in the result matrix,
• a reduction of the bit width of the first multiplicative value to obtain a reduced multiplicative value having an equal bit width as the bit width of the first register, wherein the reduction of the bit width comprises to perform a reduction operation on the multiplicative value with respect to the polynomial term of the immediate prior to performing the XOR operation, and
• an exclusive or (XOR) operation with the reduced multiplicative value and a value stored at a result matrix position stored in the third register to obtain a result value.