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US 9,960,903 B1Granted
Systems and methods for clock alignment using pipeline stages
AssigneeAltera Corporation
InventorsDana How, Carl Ebeling, Audrey Catherine Kertesz
Life of this patent
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Abstract
Systems and methods for phase detection are disclosed. Phase alignment between first and second clock signals is detected using a comparison of outputs from a collapsible pipeline and a non-collapsible pipeline.
Claims17
A phase correction system, comprising:
- a phase detector, comprising:
- a collapsible pipeline;
- a non-collapsible pipeline;
- and
- alignment detection logic that determines whether a first clock signal of a first clock is aligned with a second clock signal of a second clock, based at least in part upon a comparison between a first output of the collapsible pipeline with a second output of the non-collapsible pipeline, wherein:
- the phase detector provides an indication signal that indicates whether or not the first clock signal is aligned with the second clock signal.
3 more elements
A method, comprising:
- receiving a plurality of indications from a phase detector of an integrated circuit, the plurality of indications indicating whether or not a first clock signal provided by a first clock of the integrated circuit is tolerably aligned with a second clock signal provided by a second clock of the integrated circuit;
- and
- based upon the plurality of indications, adjusting a phase of the first clock signal, such that the first clock signal and the second clock signal are aligned;
- wherein the phase detector provides the plurality of indications based upon an accumulation of a plurality of comparisons of first outputs of a collapsible pipeline and second outputs of a non-collapsible pipeline.
1 more element
A programmable logic device, comprising:
- a first clock that provides a first clock signal;
- a second clock that provides a second clock signal;
- and
- phase detection and correction logic that provides an indication of whether or not the first clock signal is aligned with the second clock signal and corrects misalignment between the first clock signal and the second clock signal prior to processing input data provided to the programmable logic device;
- wherein each edge of the first clock signal corresponds to an edge of the second clock signal;
- and
- wherein the phase detection and correction logic corrects misalignment caused by static properties of the programmable logic device, variable distances that the first clock signal, the second clock signal or both travel, or the static properties of the programmable logic device, the variable distances that the first clock signal, the second clock signal or both travel.
4 more elements
Dependencies are inferred from the claim text.