Temporal change in data-crossing clock phase difference to resolve meta-stability in a clock and data recovery circuit

A receiver, comprising:

• sampling circuitry configured to generate data samples and crossing samples of a received signal based on a data clock signal and a crossing clock signal, respectively, which are derived from a sampling clock signal;
• a clock and data recovery (CDR) circuit configured to adjust a phase of the sampling clock signal based on the data samples and the crossing samples;
• and
• a clock manager circuit configured to adjust a relative phase between the data clock signal and the crossing clock signal from a first phase difference to a second phase difference that is less than ninety degrees, and revert the relative phase between the data clock signal and the crossing clock signal to the first phase difference after a threshold time period.

An integrated circuit (IC), comprising:

• a serializer/deserializer (SerDes) circuit coupled to a transmission channel;
• and
• a receiver, disposed in the SerDes circuit, configured to obtain a received signal from the transmission channel, the receiver including:
• sampling circuitry configured to generate data samples and crossing samples of the received signal based on a data clock signal and a crossing clock signal, respectively, which are derived from a sampling clock signal;
• a clock and data recovery (CDR) circuit configured to adjust a phase of the sampling clock signal based on the data samples and the crossing samples;
• and
• a clock manager circuit configured to adjust a relative phase between the data clock signal and the crossing clock signal from a first phase difference to a second phase difference that is less than ninety degrees, and revert the relative phase between the data clock signal and the crossing clock signal to the first phase difference after a threshold time period.