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US 9,960,788 B2Granted
Memory controller, semiconductor memory device, and control method for semiconductor memory device
AssigneeToshiba Memory Corporation
InventorDaisuke Fujiwara
Life of this patent
Estimating the term…
Abstract
A memory controller is a memory controller including an encoder that product-codes, with a linear code, data to be recorded in a memory section and a decoder that decodes product-coded data read out from the memory section. The encoder and the decoder share a parity generation circuit including a plurality of remainder calculating and retaining sections, each including a remainder calculation circuit by a generator polynomial and a retaining circuit that retains an output of the remainder calculation circuit.
Claims14
A memory controller comprising:
- an encoder that product-codes, with a linear code, data to be recorded in a memory section, the product code being a two-dimensional product code by a first code and a second code;
- a decoder that decodes product-coded data read out from the memory section;
- a first parity generation circuit that performs coding processing by the first code, generates a parity of the first code, and includes a plurality of remainder calculating and retaining sections, each including a remainder calculation circuit based on a generator polynomial and a retaining circuit that retains an output of the remainder calculation circuit;
- and
- a second parity generation circuit that is shared by the encoder and the decoder, performs coding processing by the second code, and generates a parity of the second code, wherein
- the coding processing by the second code is performed together with the coding processing by the first code,
- the parity of the second code is retained in each retaining circuit,
- decoding processing by the second code is performed together with decoding processing by the first code,
- the remainder calculation circuit is a linear feedback register, and
- the retaining circuit is a flip-flop.
7 more elements
A semiconductor memory device comprising:
- a memory section;
- and
- a memory controller including:
- an encoder that product-codes, with a linear code, data to be recorded in the memory section, the product code being a two-dimensional product code by a first code and a second code,
- a decoder that decodes product-coded data read out from the memory section,
- a first parity generation circuit that performs coding processing by the first code, generates a parity of the first code, and includes a plurality of remainder calculating and retaining sections, each including a remainder calculation circuit based on a generator polynomial and a retaining circuit that retains an output of the remainder calculation circuit;
- and,
- a second parity generation circuit that is shared by the encoder and the decoder, performs coding processing by the second code, and generates a parity of the second code, wherein
- the coding processing by the second code is performed together with the coding processing by the first code,
- the parity of the second code is retained in each retaining circuit,
- decoding processing by the second code is performed together with decoding processing by the first code,
- the remainder calculation circuit is a linear feedback register, and
- the retaining circuit is a flip-flop.
10 more elements
Dependencies are inferred from the claim text.